first commit
add Manifest files and packages
all: major reorganization of files
hdl/*: update new DSP chain with TBT, FOFB and monit data rates

Also, some minor improvements were done, like some
multi-path FIR filter implementations (sysgen option)
and reorganization of some subsystems
models/*: update main DSP model and minor model improvements
hdl/*: fix monit rate attenuation and reduce FPGA resources used
models/*: update sysgen model to fix monit rate
scripts/*: monit rate filters now have integer filtering
hdl/*: fix monit stage position attenuation
models/ddc_bpm_476_066.mdl: update sysgen model
models/ddc_bpm_476_066_hw_cosim.mdl: update hw cosim sysgen model
models/*: add backup models (will be deleted)
models/round_gain.mdl: add custom subsystems
models/tests/*: update monit test model
hdl/*: (1/2) more accurate CORDIC calculation
models/*: (2/2) more accurate CORDIC calculation
hdl/*: (1/3) massive dsp changes

* Changed to a Time-division multiplexing approach.
	We are using a 2-multilplexed stream scheme for
	high frequencies (ADC rate) and a 4-multiplexed
	stream scheme for all the other lower rates.

* Oversampling rate of 2 relative to ADC rate.
	Now, a 2xADC rate clock is used for all the
	DSP chain. It allows for a reduced number of
	resources usage	at higher rates.

* Fix delta-sigma pre-divider FIFO buffers

* Add 25-bit multipliers for Kx, Ky and Ksum (position
measurement constants)

* Lower order of BPF at the beggining of the chain, in order
to reduce the number of FPGA resources used (mainly DSP48E1).
Also, we are using an oversample rate of 2, so, rougly, 2 times
less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.
models/*: (2/3) massive dsp changes

* Changed to a Time-division multiplexing approach.
	We are using a 2-multilplexed stream scheme for
	high frequencies (ADC rate) and a 4-multiplexed
	stream scheme for all the other lower rates.

* Oversampling rate of 2 relative to ADC rate.
	Now, a 2xADC rate clock is used for all the
	DSP chain. It allows for a reduced number
	of resources usage at higher rates.

* Fix delta-sigma pre-divider FIFO buffers

* Add 25-bit multipliers for Kx, Ky and Ksum
	(position measurement constants)

* Lower order of BPF at the beggining of the chain,
	in order to reduce the number of FPGA resources
	used (mainly DSP48E1).Also, we are using an
	oversample rate of, so, rougly, 2 times
	less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.
scripts/*: (3/3) massive dsp changes

 * Changed to a Time-division multiplexing approach.
         We are using a 2-multilplexed stream scheme for
         high frequencies (ADC rate) and a 4-multiplexed
         stream scheme for all the other lower rates.

 * Oversampling rate of 2 relative to ADC rate.
         Now, a 2xADC rate clock is used for all the
          DSP chain. It allows for a reduced number
          of resources usage at higher rates.

  * Fix delta-sigma pre-divider FIFO buffers

  * Add 25-bit multipliers for Kx, Ky and Ksum
          (position measurement constants)

  * Lower order of BPF at the beggining of the chain,
         in order to reduce the number of FPGA resources
          used (mainly DSP48E1).Also, we are using an
          oversample rate of, so, rougly, 2 times
          less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.
scripts/*: add missing scripts and cosmetic changes