Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Updated simlib to new $mem/$memwr interface
Changes to "memory" pass for new $memwr/$mem WR_EN interface
changes in verilog frontend for new $mem/$memwr WR_EN interface
improved opt_reduce for $mem/$memwr WR_EN multiplexers
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
Merged new $mem/$memwr WR_EN interface