msm: bam_dmux: modify DL low memory algorithm

Bam_dmux maintains a pool of dynamically allocated buffers for the BAM DMA
engine to use as destination memory for Downlink (DL) data.  The allocation
requests for the buffers are done using flags to indicate delays are
tolerable and either the memory or an error should be returned immediately
to bam_dmux as the buffers are normally allocated within various hot paths
inside of the driver.  If a low memory allocation failure is encountered
when attempting to replenish the pool of buffers, bam_dmux will either
attempt the memory allocations later when the next scheduled pool refilling
occurs if there is at least one buffer remaining in the pool, or will
schedule a delayed task to retry the buffer allocation until atleast one
buffer can be put into the pool.

This mechanism of handling low memory situations has two flaws.  First, the
allocation type used by bam_dmux does not trigger the standard low memory
recovery mechanism within the memory management subsystem.  Second, the
peripeheral on the otherside do the DMA engine has a limited hardware based
flow control mechanism that will not release flow control with only one
buffer queued to the DMA engine.

To assist in system recovery, and avoid a data stall, create a cold path
that is tolerant of memory allocation delays and is triggered when the hot
path encounters an allocation failure.
mach-msm:bus_config:fix possible missing error check

There is a possibility of msm_bus_board_get_iid returning the error.
ERROR check is required before proceeding with the msm_bus_get_fabric_device

CRs-Fixed: 588802
Change-Id: I1353ed1b2505b117b61b72600e74b5d68d0bc508
Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
driver core: fix possible missing of device probe

Inside bus_add_driver(), one device might be added(device_add()) into
the bus or probed which is triggered by deferred probe
just after completing of driver_attach() and before
'klist_add_tail(&priv->knode_bus, &bus->p->klist_drivers)',
so the device won't be probed by this driver.

This patch moves the below line

	'klist_add_tail(&priv->knode_bus, &bus->p->klist_drivers)'

before driver_attach() inside bus_add_driver() to fix the
problem.

CRs-Fixed: 588802
Change-Id: I9250b399d57a89870d1df220b97fdca275e2e1a9
Signed-off-by: Ming Lei <ming.lei@canonical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Git-commit: 190888ac01d059e38ffe77a2291d44cafa9016fb
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: wlan: Add VHT80 support on db.txt

Adding support for VHT80 on db.txt

Git-commit: 342e794bf4130b624939504e97169c6d41bec011
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-regdb.git
Author: Luis R. Rodriguez <mcgrof@do-not-panic.com>
Date: 2013-07-17 02:18:42 (GMT)

CRs-Fixed: 557666
Change-Id: I91ed6f4d52a7b7bea93047f14455cc11b9f203ea
Acked-by: Tushnim Bhattacharyya <tushnimb@codeaurora.org>
Signed-off-by: Mihir Shete <smihir@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
defconfig: remove support for /dev/mem and /dev/kmem on perf builds

Keeping /dev/mem and /dev/kmem exposed to userspace allows userspace
to peek/poke to these areas and is a security risk. Remove support for
/dev/mem and /dev/kmem on perf builds.

Change-Id: I630101c40c806cc6682573d070964d79ca36bd57
CRs-Fixed: 530719
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Setup a3xx protection in its start function

Setup the protection registers for a3xx towards the end of its
start function instead of doing it in generic ringbuffer start

Conflicts:
	drivers/gpu/msm/adreno_ringbuffer.c

Change-Id: I66df496afa5d1fdf7dea790306f5358c2098674d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Enable protected register mode for A3XX

Turn on protected register mode for the A3XX GPU family and add 0x63
(RBBM_INT_0_MASK) to the list of protected registers.

Conflicts:
	drivers/gpu/msm/adreno.h
	drivers/gpu/msm/adreno_a3xx.c
	drivers/gpu/msm/adreno_ringbuffer.c

Change-Id: Ic0dedbad10ebfa6eb6d3d815b5aa9b6b6f0e8e35
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Protect SMMU registers from being written by the GPU

Put the SMMU register range in protected mode to shield them from
IB1/IB2 writes from userspace.

CRs-Fixed: 599971
Change-Id: Ic0dedbad8c03fc1c54ff73221231e2440d3c34dd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Print the register that causes a protected mode error

When we get a protected mode error print out the register information
that caused the exception.

Change-Id: Ic0dedbad4f586c5715669226619b51665ef9681f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Protect CP_STATE_DEBUG_INDEX

Put CP_STATE_DEBUG_INDEX and CP_STATE_DEBUG_DATA under protection
to keep it from being written from an IB1. Doing so however opens
up a subtle "feature" in the microcode: memory read opcodes turn off
protected mode in the microcode to do the read and then turns it
back on regardless of the initial state. This is a problem if the
memory read happens while protected mode is turned off and then we
try to access a protected register which then complains and goes boom.

To account for this irregularity explicitly turn back off protected
mode in all the places where we know this will be a problem.

Conflicts:
	drivers/gpu/msm/adreno.c
	drivers/gpu/msm/adreno_a3xx.c

Change-Id: Ic0dedbad1397ca9b80132241ac006560a615e042
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Mark the IOMMU setstate memory as read only

Mark the IOMMU setstate memory as read only in the pagetable.

Change-Id: Ic0dedbadb19e499c749cd744c3e89be3bcb4c2a2
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Enable protected register mode for A2XX

Turn on protected register mode for the A2XX GPU family.

Change-Id: Iecf88d648c9f86faef4fa53e90c2ce81101c58fa
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: don't use sscanf()

Friends do not let friends use sscanf().

CRs-Fixed: 563605
Change-Id: Ic0dedbad56af5bbee4fc833701d8bc93b118efa9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Ananta Kishore K <akollipa@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
Revert "Execute shader on wakeup from power collapse"

This reverts commit 28eabf6987637c6c438c461aa31ce25e0f7edcc5.

Conflicts:

	drivers/gpu/msm/adreno.c
	drivers/gpu/msm/adreno.h
	drivers/gpu/msm/adreno_a3xx.c
	drivers/gpu/msm/adreno_ringbuffer.c

Change-Id: I0a979f33d9030546d1e72b63cff88d269f63a4c7
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Increase the timeout value for fault detection

Increment the timeout value for detecting faults from 50ms to
200ms. The fault detection mechanism is a backup to hardware
fault detection. 50ms is small since it has been observed that
this mechanism triggers false positives with 50ms.

CRs-Fixed: 672164
Change-Id: I8f382051e06bdc47f152309a2868092e1980604e
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
msm: kgsl: Force the ME off before reading the microcode

On A3XX reading the microcode while the CP is running is dangerous
beyond words.  By setting the offset address for the read, we are
essentially changing the instruction pointer for the ME while it
is running causing opcode errors, gpu faults and/or system errors.

We do not want to stop the CP at the beginning of the snapshot
process beacuse doing so changes the RBBM status and the state of
the CP registers which may damage the debug effort.  But by the
time we get to the microcode read we no longer care about the state
of the registers so we can freely halt the ME just before starting
the read.

Conflicts:
	drivers/gpu/msm/adreno_a3xx_snapshot.c

Change-Id: Ic0dedbad85d7ec26915f054dd597e226e8101a29
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
qup_i2c: set up node before calling of_i2c_register_devices

Device-tree framework for I2C expects adapter of device's
of_node to be initialized before adding I2C slave devices
on the bus.

Change-Id: I64af0b6bafb71ec94ad5acfe3034e9be887ebc47
Signed-off-by: Amy Maloche <amaloche@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
qup_i2c: Add runtime PM support to I2C QUP controller

Runtime PM is used to turn clocks on and off when the
controller is not in use. When the controller is used
for messaging, pm_runtime_get_sync is called before
sending the message. pm_runtime_mark_last_busy and
pm_runtime_put_autosuspend are called when message
is sent and/or response is received.

Change-Id: Icb1d6e6ad222663c9a3598da10bdc154845083a0
CRs-Fixed: 406910
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Signed-off-by: Manish Kumar <manishku@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
qup_i2c: Avoid potential panic issue

I2c register access is happening in isr before check
PM runtime status. This can lead to potential hang because of
unwanted interrupts and i2c clocks are off.

Update the i2c driver code to have register access
after PM runtime status check.

CRs-Fixed: 454710
Change-Id: I11a3d8df24c514205203f24be8e08d7c1ea1a7b8
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>
qup_i2c: Update clock ready check condition

While doing i2c transfer that involved write and
immediate read, the driver will put the controller
to RESET and do an immediate read before the write completes.
This issue is hard to produce internally because clock stretch
from slave device is involved during the failure time. CLK
state in QUP status register will be FORCED_LOW_STATE.

O/p fifo empty check added to determine clock idle.

CRs-Fixed: 455743
Change-Id: I51c1d9f9de42381fc85710e9185aa4177f6cd302
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: juanxincai521 <2061287898@qq.com>