msm: mdss: Fix BWC width alignment

BWC src width is segmented into 16 aligned RAUs. The segmentation
into 16 RAUs needs to be rounded up for corner cases.

Change-Id: Idbf675d7adfb45cb28e6c456dd4fd7c7f41ea280
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
msm: mdss: Make notify update waits interruptible

Wait for completion in notify update call are uninterruptible
causing excessive delay during suspend cases. Making them
interruptible.

Change-Id: I1a4ff6ce3e0add21d4e46a41372b076b277d10f5
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Don't call pan_idle for MSMFB_OVERLAY_PREPARE ioctl

We keep calling MSMFB_OVERLAY_PREPARE for each composition
cycle, even if there are no changes in params. Because of this
we can hit performance degradation due to pan idle wait.
This change removes pan_idle wait for prepare call.

CRs-Fixed: 600539
CRs-Fixed: 608848
Change-Id: Ie99f4dbc4671caf9bfbd49bd9b200c3180002d56
Signed-off-by: Radhika Ranjan Soni <rrsoni@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_fb.c
ARM: dts: mdss: Add boolean property for LUT readability

LUT read is not supported by hardware in the case of msm8226.
Adding property to dtsi file to denote the absense of support
for read in hardware.

Change-Id: I29cf869af4135e1199bc0feb4369700b994520ec
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Correct ARGC read write for all DSPP

Currently ARGC read write is done for DSPP0 irrespective of
dspp_num, as the dspp_num corresponding to the block provided
is not calculated.

Added the calculation of the dspp_num to get correct address
of ARGC registers.

Change-Id: Id787e76debb26d23d75d3cdb859a697b6f0016f5
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Remove init phase programming

Init phase should only be programmed to a non zero value only through
a user program. Default value of zero is programmed by the driver to
avoid hardware hangs

Change-Id: Iff99394d2f3a937c5bb4456c2f7ca5669a5c732b
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
(cherry picked from commit 3ddf2d1beee42354e28f1719849dcc0d0b06c5a1)
mdss: Add newline to VSYNC timestamp for mdp3 driver

This makes sure that the userspace correctly interprets the end
of the vsync timestamp.

CRs-Fixed: 639039
Change-Id: I8a0810283a42a9c39a3c8fe36b862bbfd3ecdbea
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
mdss: mdp3: Remove extra call to clk_prepare

clk_prepare got moved inside mdp3_clk_update. Prior to this patch
unprepare would never be called successfully.

Change-Id: I28ab035b42d433f379d63748ac4f506a8575ea66
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
msm: mdss: Turn off backlight while power off

Turn off the backlight while shut down panel as it
could show white flicker depending on the panel.

Change-Id: Ic5d4e97e70c87e5b6e956e27a766136610d6f345
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
msm: mdss: Acquire shared lock after getting frame on wfd

Currently there is a deadlock when wfd and rotation is done
simultaneously and trying to acquire the shared lock. To
prevent this, acquire shared lock after rotated frame is
ready for wfd.

Change-Id: I3865f02c345ddadd985ee35134454a789936a79a
Signed-off-by: Anusha Koduru <kanusha@codeaurora.org>
mdss: Dynamic timeout calculation for cmd stop

Time out condition was hard coded to 60 fps. If dynamic fps
feature was used, an invalid timeout might occur.

Change-Id: I0abe52416c10ef4ae0af6f541d22c66f6c8a6b5e
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
msm: mdss: Move histogram completion initialization to pp_init

The histogram completion structure only needs to be initialized fully
once, and this can be done when the pp resource structure is created.
Otherwise, when enabling the histograms, it is sufficient to use the
reusable INIT_COMPLETION, in order to avoid any wait_queue errors.

Change-Id: Id4bfb19c91bd5ab07c01a5eb347ba50621fe8a97
Signed-off-by: Benet Clark <benetc@codeaurora.org>
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
defconfig: Set noop as default schedular for faster bootup

We will change to row from userspace

Change-Id: Ie5b2858afb23c9977cc4d8a202adc105578115db
qseecom: update clock ref count when bus scaling timer is running

When there are multiple enable/dislable clock operations, ce clock
ref count is not updated correctly when the timer to disable clock
is running. Specifically, the ref count is not decreased when the
old operation is finished and then we reset clock for the new enable
clock. Thus, the ce clock is not disabled after all operation are
completed due to incorrect clk ref count. We make a change to
decrease clock reference count before reset timer, when the timer
is running, then clock is disabled when all ce clock operations
finish and the timer expires.

Change-Id: If71fd526acd9a74bf21731841fae0b98e76a89b5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: change qseecom bus scaling timer operation

To ensure ce clock is not disabled before tz operation is completed,
we delete the old timer when tz side operation begins, and then add
a new timer after tz operation is completed.

Change-Id: I4bc8fe3d9305cc1ed5db8e6490832fcc790ef3d7
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Validate the pointer returned by ion_import_dma_buf

Do a "IS_ERR_OR_NULL" check for the return value of
ion_import_dma_buf.

Change-Id: Iaac8b59b1f076d002430e0e6aba055bd88c83ed7
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Revert "qseecom: change qseecom bus scaling timer operation"

This reverts commit 06418b79767c16f0637c23e516ccd0b7ece51dd2.

Change-Id: I59a93084584e7a2608d8af097bdbb50391c5a052
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: change qseecom bus scaling timer operations

To ensure ce clock is not disabled before tz operation is completed,
we delete the old timer when tz side operation begins, and then add
a new timer after tz operation is completed.

Change-Id: I4bc8fe3d9305cc1ed5db8e6490832fcc791ef3d7
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Ensure CE clk is managed properly

clk access ref count is not updated correctly when issuing a
request that requires enabling clk. this results in leaving the
clk on during regular operation resulting in failure of the
device to go into low power mode.

Change-Id: I80232433ff09277fe83d78142dcec75e7493d96e
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
qseecom: Change pr_warning message to pr_debug

Change warning message to debug message to reduce the excessive logging.
These changes are applicable only if any process is trying to interrupt
the blocking listener services.

Change-Id: Ie1c9af0daf16ef2c39e198f30b0151e2246d79e3
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>