MachO: support N_INDR aliases in assembly files.

This makes LLVM create N_INDR aliases (to be resolved by the linker) when
appropriate.

rdar://problem/15125513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209894 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: use AAPCS-style prologues for embedded MachO.

Darwin prologues save their GPRs in two stages: a narrow push of r0-r7 & lr,
followed by a wide push of the remaining registers if there are any. AAPCS uses
a single push.w instruction.

It turns out that, on average, enough registers get pushed that code is smaller
in the AAPCS prologue, which is a nice property for M-class programmers. They
also have other options available for back-traces, so can hopefully deal with
the fact that FP & LR aren't adjacent in memory.

rdar://problem/15909583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209895 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAG: skip barriers for unordered atomic operations

Unordered is strictly weaker than monotonic, so if the latter doesn't have any
barriers then the former certainly shouldn't.

rdar://problem/16548260

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209901 91177308-0d34-0410-b5e6-96231b3b80d8
[pr19636]  Fix known bit computation in urem instruction with power of two.
Patch by Andrey Kuharev.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209902 91177308-0d34-0410-b5e6-96231b3b80d8
PR19753: Optimize comparisons with "ashr exact" of a constanst.

Patch by suyog sarda.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209903 91177308-0d34-0410-b5e6-96231b3b80d8
MachO: move test to ARM directory.

This test specifies an ARM triple, so it needs ARM as a registered
target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209905 91177308-0d34-0410-b5e6-96231b3b80d8
Fix MIPS exception personality encoding.

For MIPS, we have to encode the personality routine with
an indirect pointer to absptr; otherwise, some link warning
warning will be raised, and the program might crash in some
early MIPS Android device.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209907 91177308-0d34-0410-b5e6-96231b3b80d8
Make bitcast, extractelement, and insertelement considered cheap for speculation.

This helps more branches into selects. On R600,
vectors are cheap and anything that helps
remove branches is very good.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209914 91177308-0d34-0410-b5e6-96231b3b80d8
fixed typo


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209916 91177308-0d34-0410-b5e6-96231b3b80d8
added link to CMake page


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209918 91177308-0d34-0410-b5e6-96231b3b80d8
Roll DbgVariable::setMInsn into the constructor. No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209920 91177308-0d34-0410-b5e6-96231b3b80d8
fixed more typos


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209921 91177308-0d34-0410-b5e6-96231b3b80d8
Separate the check for blend shuffle_vector masks

Summary:
Separate the check for blend shuffle_vector masks into isBlendMask.
This function will also be used to check if a vector shuffle is legal. No
change in functionality was intended, but we ended up improving codegen on
two tests, which were being (more) optimized only if the resulting shuffle
was legal.

Reviewers: nadav, delena, andreadb

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209923 91177308-0d34-0410-b5e6-96231b3b80d8
Rename CreateTLOF->createTLOF to match the rest of the file and the
rest of the targets with a similar function name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209926 91177308-0d34-0410-b5e6-96231b3b80d8
isSVR4ABI() returned !isDarwin() so just move that to the else
block and remove the unreachable code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209927 91177308-0d34-0410-b5e6-96231b3b80d8
Convert a vselect into a concat_vector if possible

Summary:
If both vector args to vselect are concat_vectors and the condition is
constant and picks half a vector from each argument, convert the vselect
into a concat_vectors.

Added a test.

The ConvertSelectToConcatVector is assuming it doesn't get vselects with
arguments of, for example, <undef, undef, true, true>. Those get taken
care of in the checks above its call.

Reviewers: nadav, delena, grosbach, hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209929 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Add two combine rules to simplify dag nodes introduced during type legalization when promoting nodes with illegal vector type.

This patch teaches the backend how to simplify/canonicalize dag node
sequences normally introduced by the backend when promoting certain dag nodes
with illegal vector type.

This patch adds two new combine rules:
1) fold (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
        (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)

2) fold (BINOP (shuffle (A, Undef, <Mask>)), (shuffle (B, Undef, <Mask>))) ->
        (shuffle (BINOP A, B), Undef, <Mask>).

Both rules are only triggered on the type-legalized DAG.
In particular, rule 1. is a target specific combine rule that attempts
to sink a bitconvert into the operands of a binary operation.
Rule 2. is a target independet rule that attempts to move a shuffle
immediately after a binary operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209930 91177308-0d34-0410-b5e6-96231b3b80d8
Have the TLOF creation take a Triple rather than needing a subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209937 91177308-0d34-0410-b5e6-96231b3b80d8
delete dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209938 91177308-0d34-0410-b5e6-96231b3b80d8
[TSan] Behave the same for functions w/o sanitize_thread attribute and blacklisted functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209939 91177308-0d34-0410-b5e6-96231b3b80d8