samus_pd: Add workaround for unwanted pericom resets

Our pericom charge detectors can reset themselves on rapid charger plug
/ unplug, which resets the interrupt enable to the power-on default
(off). Work around this problem by re-enabling pericom interrupts from
the VBUS interrupt.

BUG=chrome-os-partner:33823
TEST=Manual on samus. Rapidly plug + unplug charger, verify that Pericom
continues to trigger interrupts.
BRANCH=Samus

Change-Id: I7370525e28c59bdde3765e52523d5158d1d6175d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231700
Reviewed-by: Alec Berg <alecaberg@chromium.org>
ryu_sh: Add Makefile in board directory.

To match other boards, add a link to Makefile in board/ryu_sh.

BRANCH=ToT
TEST=compile
BUG=None

Change-Id: I19c58e2fd221ddf2e607f6a732e2e6229daedd1f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231983
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
cr50: Replaced ww with md EC cli

Supported memory commands are: rw and md.
 - rw: for read/write a word
 - md: for memory display

Usage: rw addr [value]
Usage: md addr [num of words (4B)]

BRANCH=none
BUG=none
TEST="make BOARD=cr50" and "md 0 100"

> md 0 100
[00000000] : 00018000 0000011d 00000101 00000101
[00000010] : 00000101 00000101 00000101 00000101
...

Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Change-Id: I1de8c690cca006ec3aae42d4e6bd0ba30f7c3238
Reviewed-on: https://chromium-review.googlesource.com/231398
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
cr50: update for 12/03 hardware release

Update the register definitions.
Note: UART pin muxing has changed.

Should be the final version for rev A1.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make BOARD=cr50
load the software and see the console working.

Change-Id: Id17f7e00f75a14ab296c745b100b0085aaa79011
Reviewed-on: https://chromium-review.googlesource.com/233108
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
g: add core reset

Until we implement a proper reset of the microcontroller,
add a reset of the Cortex-M3 CPU core in system_reset() in order to
avoid getting stuck in a weird loop if we get a panic.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=trigger a data abort and verify we are not going into a panic loop.

Change-Id: Ie046379e6a9469bd683fa774cdc9abb10a14e8f1
Reviewed-on: https://chromium-review.googlesource.com/233109
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Remove extra EAh at end of RW image.

EAh is used at the end marker for calculating hash in EC.
The extra EAh make hash calculated by EC different from calculated in host
by sha256sum for the RW image. The RO image is fine.

Fix a comment, no A,B images anymore.

BUG=chromium:438326
TEST=Check sha256sum is similar for Ryu EC image.

On EC console
> hash rw
[28.740271 hash start 0x00010000 0x0000ea24]
> [28.938875 hash done e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534]
sha256sum of built image:
sha256sum build/ryu_p1/ec.RW.flat
e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534
build/ryu_p1/ec.RW.flat

TEST=Check firmware upgrade still works:
Using a modify version of coreboot with
- ryu_p1 as main ec firmware
- code to reenable SW sync: CL:233222
Ryu with an older image:
cros_ec_init: CrosEC protocol v3 supported (128, 128)
Google ChromeOS EC driver ready, id 'ryu_p1_v1.1.2570-942248a'
Clearing the recovery request.
VbEcSoftwareSync(devidx=0)
EC hash:e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534
EC-RW hash address, size are 0x835b4ff8, 32.
Hash = b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
Expected hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
EC-RW firmware address, size are 0x837f9374, 59924.
VbEcSoftwareSync() - expected len = 59924
Computed hash of expected
image:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
VbEcSoftwareSync() updating EC-RW...
VbEcSoftwareSync() jumping to EC-RW
VbEcSoftwareSync() jumped to EC-RW
VbEcSoftwareSync() in RW; done

Check that at next reboot the firmware is not upgraded:
cros_ec_init: CrosEC protocol v3 supported (128, 128)
Google ChromeOS EC driver ready, id 'ryu_p1_no_version'
Clearing the recovery request.
VbEcSoftwareSync(devidx=0)
EC hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
EC-RW hash address, size are 0x835b4ff8, 32.
Hash = b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
Expected hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46
VbEcSoftwareSync() in EC-RW and it matches
BRANCH=ToT

Change-Id: I2db275a16b16fbcea95f53287e95104ba921593e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232952
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
pd: move get_info to common file.

get_info command needs to be used by all type-C accessories that would
entertain being updated in the field.  This CL migrates function to
common/usb_pd_protocol.c for other boards to use.

Signed-off-by: Todd Broch <tbroch@chromium.org>

BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,

Using
  ectool --name=cros_pd infopddev <0|1>

Port:1 Devid 1.1 Hash:  0x00ec9619 0x811f3e68 0x4b90c8e9 0xd5b98fa8 0xfd373777
Port:1 Devid 3.0 Hash:  0x682fd366 0x7213f55e 0xddefb802 0xbedfec42 0x5cdcc226
Port:0 Devid 4.0 Hash:  0x57b1e4e0 0x7204075f 0x65c0fa72 0xdcca15ed 0xf3231237

Change-Id: Iffa8699056351f62cf90fdecbc7ef5cee81e67bb
Reviewed-on: https://chromium-review.googlesource.com/226891
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
pd: ectool: Increase sleep after PD reboot for flashing.

Longer sleep is needed to provide enough time for USB-PD devices to:
  1. boot RO & validate RW
  2. Initialize PD
  3. Enter Alternate mode (GFU)

Signed-off-by: Todd Broch <tbroch@chromium.org>

BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,
Flashing RW on dingdong via,
  ectool --name cros_pd flashpd 3 1 dingdong.ec.RW.bin
works

Change-Id: Id9c6f3907022f62bf887dfefc23b51d070b331b8
Reviewed-on: https://chromium-review.googlesource.com/233023
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
usb_pd: Battery PDO protocol definition errors

PDO_BATT_OP_POWER() inadvertently adopted its calculation from OP_CURR,
resulting in different division bases: 250mW vs 10mA.

BUG=none
BRANCH=none
TEST=make buildall

Change-Id: Ia03681d72fba325899566039c275e2776b212793
Reviewed-on: https://chromium-review.googlesource.com/233064
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Bernard Shyu <bernard_shyu@bizlinktech.com>
Tested-by: Bernard Shyu <bernard_shyu@bizlinktech.com>
pd: dingdong/hoho: Fix hard reset recovery timeout.

dingdong/hoho have no capability to measure VBUS which is advantageous
in determining what timeouts to honor.  Previously we simply assumed
vbus was on and that made things happy until,

  e0c80ac pd: on hard reset go to a hard reset recovery state

which introduced proper handling around sink & source reset recovery.

With VBUS assumed 'on' this leads to short timeouts chosen
(PD_T_SAFE_0V) which in turn causes sink to resend hard resets before
source has had time (PD_T_SRC_RECOVER) to handle request.

This change creates config CONFIG_USB_PD_NO_VBUS_DETECT for devices
without the capability to account for lack of VBUS detect.

Signed-off-by: Todd Broch <tbroch@chromium.org>

BRANCH=samus
BUG=chrome-os-partner:34090
TEST=manual
from samus_pd 'pd 1 flash reboot' is successful

Change-Id: I9ef9b0115c7be6c56c64556d2ce8c296f95c614e
Reviewed-on: https://chromium-review.googlesource.com/233024
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
pd: Re-factor common flash vdms.

CL to migrate the flashing VDMs from zinger's custom vdm to
common/usb_pd_flash.c such that other updateable type-C devices can
share.

Additionally adds gaskets to call standard runtime flashing facilities
for USB-PD devices using it.

Signed-off-by: Todd Broch <tbroch@chromium.org>

BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,

Try following:
    1. From samus_pd console w/ zinger in port 1

    pd 1 flash version
    pd 1 flash reboot
    pd 1 flash info

    2. From samus linux prompt  w/ zinger in port 1

    ectool --name cros_pd flashpd 1 1 <zinger RW payload>

    Reading 16384 bytes from
    /usr/local/zinger_v1.1.2528-d809e42.ec.RW.bin...
    Erasing expected RW hash
    Rebooting
    Erasing RW flash
    Writing RW flash
    Rebooting PD into new RW
    Complete

    3. Repeat 1&2 above on hoho & dingdong.

Change-Id: I018055fa9de128f937c57debdc21dea026137bcf
Reviewed-on: https://chromium-review.googlesource.com/231835
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
pd: dingdong/hoho: Increment device ID minor rev.

Incrementing minor from 0 -> 1 to signify devices with this firmware
are field updateable.

Signed-off-by: Todd Broch <tbroch@chromium.org>

BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual

  # on dingdong
  ectool --name cros_pd infopddev 1
  Port:1 DevId:3.1 ...

  # on hoho
  ectool --name cros_pd infopddev 1
  Port:1 DevId:4.1 ...

Change-Id: I2e55b4371131c39a22e917c02d43a26977ea3a93
Reviewed-on: https://chromium-review.googlesource.com/233270
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
g: fix hwtimer event deadline

We were losing timer events because usecs_to_ticks(deadline) was
clipping the value when deadline was larger than 0x08888888 (deadline is
a timestamp rather than a delay).
The computation of the timer deadline has been modified to avoid the
clipping issue.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:34347
TEST=run on Cr50 with the watchdog activated and no longer see watchdog
warnings.
Run the "timer_calib" test and see that the 1s sleep is 1000038 us :
make BOARD=cr50 tests
fhl ../build/cr50/timer_calib/timer_calib.RO.hex

Change-Id: Id2200a89eb1b72099e536291af321609b24b4777
Reviewed-on: https://chromium-review.googlesource.com/233531
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
g: add watchdog driver

Implement a driver to trigger a watchdog reboot if we are stuck
somewhere. Also display a nice warning when we reach half of the
watchdog period.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=On the console, type "waitms 500" and see nothing,
type "waitms 2000" and see the watchdog warning.
Type "waitms 4000" and see the warning, the platform rebooting.

Change-Id: Iac5d0100febd5eab1ae6cfac5a47ff728ebda3a6
Reviewed-on: https://chromium-review.googlesource.com/233430
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
g: update reset code

- record and display reset cause
- add the hard reset option
- add the scratchpad to store values across reboots.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:33818
TEST=On the console command line, chech the "[Reset cause: xxx]" string
- for the initial reset cause
- use "waitms 4000" to trigger a watchdog reset
- use "reboot soft"
- use "reboot hard"
The "utils" test is now building and passing.

Change-Id: I68c7096e5b7bfd102be89fd8eef6fe20da37a6f8
Reviewed-on: https://chromium-review.googlesource.com/233581
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
g: update version string

Build the hardware version string from the register definitions,
so I no longer forget to update it.
Check it at runtime against the build version registers.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=On the console command line,
type "version" and see the following string:
"Chip:    g cr50 A1 20141203_224409"

Change-Id: I6d902780d42f2dd18a57ccc08fd4ba4fee5ebc7c
Reviewed-on: https://chromium-review.googlesource.com/233582
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Speedy: add initial speedy support

Copy from Jerry for now.

BUG=chrome-os-partner:33269
TEST=emerge-veyron_speedy chromeos-ec
BRANCH=None

Change-Id: I8375e1e23de5dbae0d1c579770d88e81223debce
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233795
Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
pd: before sysjump send soft reset and then disable PD comms

Before sysjump we need to send a soft reset to any attached devices
and then disable PD communication so that we don't re-negotiate again
before the sysjump. This will guarantee expected message ID is cleared
for after the sysjump.

This also moves executing soft reset from before sending the soft reset
command to after the port partner accepts a soft reset.

BUG=none
BRANCH=samus
TEST=test on samus. without this change, when sysjumping the PD MCU
has time to re-negotiate (at least partially) before the sysjump, which
causes various problems. with this change, when sysjumping, the PD
MCU sends soft reset, and then does not send anything else.

Change-Id: Id7a60c62c8908ee4ab33dfbe995ef136b0aa83de
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233751
USB: Add setup packet struct and parsing routine

This can be used by interface specific EP0 setup
packet callbacks.  The USB-SPI bridge will use
this to handle enabling and disabling the bridge.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: I3f3db65934707243f54bed9e093f376b6978d271
Reviewed-on: https://chromium-review.googlesource.com/232367
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
USB-SPI: Make global initializer names more unique

Previously it was relatively easy to collide with these
names in user code, adding the _ suffix makes that much
less likely.

Signed-off-by: Anton Staaf <robotboy@chromium.org>

BRANCH=None
BUG=None
TEST=make buildall -j

Change-Id: I997e1bc81aab4ca0b16e011bf5ff66444320c4f1
Reviewed-on: https://chromium-review.googlesource.com/232731
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>