OMAP4: ID: Chip detection for OMAP4470

Add support for detection of the next chip in the OMAP4 family: OMAP4470 ES1.0

Change-Id: I931d3df6e69fdc3ee4a307c204a68fc9b3ff519b
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
ARM: OMAP4: clock: Define 4470 flag in cpu masks

Define OMAP4470 flag in clock cpu masks.
Reuse CK_44XX clocks for 4470.

Increased 'flags' field size to fit additional CPU type.

Change-Id: I546d69495152567b2248b457172c0ab7b2782ce3
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: voltage: Add 4470 voltage definitions

Add structures containing OMAP4470 voltage supported and various
voltage dependent data for each VDD.

Data is based on Data Manual Operating Condition Addendum v0.2 for 4470.

Change-Id: I8baa6ccf26786b4ee1764fe96f312ae7fb65ccbf
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: DPLL: override for untrimmed unit

Read the value of DPLL TRIM register to check if unit is trimmed.
If it is not trimmed override OMAP4_DPLL_NWELL_TRIM_0 register
with value 0x29.

Change-Id: I5a1678860a9b663b4ce9f1f53694de9930593147
Signed-off-by: Oleksandr Kozaruk <oleksandr.kozaruk@ti.com>
OMAP4: OPP: Add 4470 OPP definitions

Add initial OPP definitions for OMAP4470.
Based on Data Manual Operating Condition Addendum v0.2 for 4470.

Change-Id: Ib3c1b3f4b69560e501b97a18cb72bd0aa0e4292f
Signed-off-by: Taras Kondratiuk <taras@ti.com>
ARM: OMAP4470: PM: Runtime checking for 4470

Add runtime checking for 4470 in those places, where
it behavior is similar to 4460.

This change will:
- allow SRAM LDO to attain retention during low power mode
- remove the static dependency between mpuss and emif

Change-Id: Ifd99fe224412259abf1288240e0846d4dc1c2ae0
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
OMAP4: clock: Reuse 4460 TS clocks for 4470

Bandgap thermal sensor in OMAP4470 has the same clock scheme as in OMAP4460.
Reuse div_ts_ck and omap_temp_sensor.0 clocks for 4470.

Change-Id: Idee2cf773b4e5d4c4ce4e8b15ddc6d1e1f82ee40
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: clock: Reuse 4460 MPU clock for 4470

OMAP4470 has the same MPU clock scheme as OMAP4460.
Reuse virt_dpll_mpu_ck clock for 4470.

Change-Id: Id3f992d1595c5cc02d316199ad999a084f623b1f
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: PM: powerdomain: Reuse 4460 MPU powerdomain for 4470

MPU powerdomain in OMAP4470 has the same characteristics as in OMAP4460.
So powerdomain stucture can be reused for 4470.

Change-Id: Ib18ae5f56b532a7ad5bdfaf67965fbe1ff5076e6
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: hwmod: Reuse 4460 HWMODs for 4470

A set of OMAP4470 harware modules is the same as in OMAP4460.
Reuse following HWMOD structures for 4470:
 - Control Module
 - Bandgap
 - Thermal sensor
 - GPIO1 bank

Change-Id: I247accdcddd06e32daad2e632830cbec2619373b
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: ID: Add runtime detection of 4470 1.5Ghz silicon

STD_FUSE_PROD_ID_1[17:16] fuse determines silicon type:
0x1 - Standard performance (1.3 GHz)
0x2 - High performance (1.5 GHz)

Change-Id: I7e37daf1d214d63b35f10fa45952485c59cbc009
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>

Conflicts:
	arch/arm/mach-omap2/board-44xx-identity.c
OMAP4: clock: Use DCC in 4470 for OPPs higher than 1GHz

OMAP4470 doesn't have a DCC issue so DCC can be used
for frequencies higher than 1GHz.

Change-Id: I76e8559b532264f01b51d7caa38ca294e8565834
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4470: OPP/voltage: Add voltage for OPPSB

OPPNT and OPPSB have the same voltage, but they should have different nTargets.
Wrong nTargets leads to instability at 1.5GHz, because voltage goes too low.

Change-Id: I698920118860cce47e76c5c03fa9c829c06454a2
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: OPP: Add High Performance CORE OPP set

OMAP4470 specification defines two sets of CORE OPPs:

   OPP  |    Low Power     | High Performance |
        | Volt | L3  | SGX | Volt | L3  | SGX |
--------+------+-----+-----+------+-----+-----+
 OPP50  | 0.96 | 100 | 154 | 0.96 | 117 | 191 |
 OPP100 | 1.13 | 200 | 307 | N/A  | N/A | N/A |
 OPP-OV | 1.23 | 200 | 384 | 1.23 | 233 | 384 |

High Performance set is enabled if CORE DPLL frequency is higher than 1600MHz.
OPP100 is absent in High Performance set.

Change-Id: Ief4c6617940365e18a0f5a22adf94a3c6f3b7192
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: clock: Extend L3 clock dependencies to cover 4470

Currently L3 OPP50 frequency is hardcoded to 100MHz.
But OMAP4470 has High Performance CORE OPP set where L3 OPP50 is 116MHz.
This patch exetends L3 clock dependencies to cover 4470 HP CORE OPP set.

Assumption made that DDRPHY freq is always 4x L3 freq.

Change-Id: I124b77d797c16ea0ccf32ba7b74a3d1c0bfe1058
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4470: TEMP_SENSOR: Fatal threshold hardware warm reset generation

On 4470 the TSHUT signal can be mapped to the device SCRM external
warm reset logic to activate the PRM.SYS_WARMIN_RST input
when a fatal temperature threshold (TSHUT_HOT) is exceeded.
Hence, a hardware warm reset can be triggered directly on
the device upon a fatal temperature threshold crossing event.

Since this feature have been added for 4470, shutdown thresholds
can be set earlier. So, additional checking has been added to prevent
multiple writing to one time writable register.

Also this patch add corresponding sysfs debug hook functions to
enable/disable hardware reset feature.

Change-Id: I260e16e2808fddc0ecb06211a74aced8c4b12a5d
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
HACK: OMAP4470: OPP: Set MPU OPP50 to 396.8MHz

Due to current clock framework implementation we shall prevent unnecessary
matching of DPLL target rate with bypass clock rate.

Otherwise DPLL will be set to bypass mode, that can give unexpected
result.

Example:
	OPP100 -> 0PP50 (assuming that IVA is not holding CORE)
 .---------------------------------------------------------------.
 . _______ _____800MHz_____                                      .
 . |     |                 \                                     .
 . | MPU |                  \______400MHz____                    .
 . |     |                                   \_____200MHz_____   .
 . |-----+-----------------------------------------------------  .
 . |mode | MPU dpll locked | MPU dpll bypass | MPU dpll bypass | .
 . |-----+-----------------------------------------------------  .
 . |     |                                                       .
 . |CORE | _______________400MHz_____________                    .
 . |_____|                                   \_____200MHz_____   .
  ---------------------------------------------------------------
				Result: OPP50 working on 200MHz

To avoid similar situations OPP50 rate will be moved from 400 to 396.8MHz.

Change-Id: I33352aa19506bbdad3cb402c167196471bbf7253
Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
OMAP4470: Added constants for 4470

List of added constants:

OMAP4470_MAX_DPLL_MULT
OMAP4470_MAX_DPLL_DIV
OMAP4470_CLKSEL_BB2D_FCLK_SHIFT
OMAP4470_CLKSEL_BB2D_FCLK_MASK
OMAP4_CM_DSS_BB2D_CLKCTRL_OFFSET
OMAP4470_CM_DSS_BB2D_CLKCTRL

Change-Id: I5416d6b8451ef86e97139cf30214c4dec774e24d
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
OMAP4470: Added ipu_fck clock implementation specific for 4470

ipu_fck clock changed in non backward compatible way: in 4470 parent for
this clock changed from ducati_clk_mux_ck to div_core_ck. So we add new
implementation specific for 4470

Change-Id: I2a0ce961761bc966dc7fcbf61bb69d3b540c4324
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
OMAP4470: Added iss_fck clock implementation specific for 4470

iss_fck clock changed in non backward compatible way: parent clock
changed from ducati_clk_mux_ck to div_core_ck. So we add new
implementation specific for 4470.

Change-Id: I18e5b4e2d653cbe340e85dac66af167f267f2d84
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>