JIT: Fix redundant MOVs in x86 trampolines

Fixes spammy log messages about redundant MOVs.
Frame: Fix a crash-on-exit on Mac OS X.

A null pointer exception is triggered when Dolphin is quit from the dock.
Eliminate some spammy log messages in MMU mode

dcbz: just don't use GetPointer, that can't be right anyways
ppcanalyst: don't print "instruction hex 0" messages in MMU mode, where ISIs
are expected.
[AArch64] Optimization in the dispatcher.

Align our dispatcher to a page so we can jump to it with a ADRP+BR pair instead of ADRP+ADD+BR.
Also make sure to save /all/ of our callee saved registers that we are supposed to save.
Requires PR #1705 prior to merging.
[AArch64] Removes ARMv8 as a generic target.

Generic flag disables the ability to have backpatching supporting.
Also compiles Dolphin with CRC instructions enabled.
[AArch64] Register cache improvements.
Adds the ability to flush the cache and maintain state.
Adds the BindToRegister ability.
Sorts register usage as callee saved used first, reduces dumping pressure when jumping to external routines/interpreter.
Adds a function to store a register, for use when flushing a register that won't be used during the rest of a block.
[ARM] Adds a ArmCommon folder.

Moves the backpatch flags and struct to a common location for ARM.
I'm sure there will be more things that use this common ARM location in the future.
[AArch64] Removes CODE_SIZE variable.

This is in a global location now which conflicts with this one.
[AArch64] Add an exception exit function with the exit location already in PC.
This will be used with idle skipping later.
[AArch64] Adds backpatching routines.
Currently supports only integer loadstores. Floating point loadstores will come later.

This system is semi based on the ARMv7 backpatching routine, where we need to initialize our backpatch routine sizes prior to actually using them so
we know we won't be overwriting any memory.
[AArch64] Implements loadstore instructions in the JIT recompiler.

These instructions are all implemented with fastmem support.
Currently loads with update are disabled due to an issue that I've yet to figure out.
I'm sure I'll figure that out later.
[AArch64] Flush registers from register cache if they won't be used again.

This requires PR #1705 and #1723 prior to merging.
[AArch64] Adds support for BindToRegister to the integer instructions.

This requires PR #1723 prior to merging.
Update Outdated Google Code References
[AArch64] Adds support for conditional continue.
Requires PR #1723 prior to merging.
[AArch64] Add partial support for cmp* instructions.

This support is as far as ARMv7's support for these instructions.
Requires PR #1728 prior to merging.
Merge remote-tracking branch 'origin/clean-up' into clean-up