stm32: common: fix missing SPI_I2S_BASE rename regression

Fix regresion from 5d4437fe43aa68a28611e9a0aecc712833230304 where
somehow not all occurrences were replaced.  I could swear it all
compiled when I was working on it :(

Reported-by: Trevor Woerner <trevor.woerner@linaro.org>
[f4] Added a 25mhz clock
Renamed README to README.md to be recognized as Markdown by GitHub
Markdowned README.md
vf6xx: initial add of Vybrid VF6xx support

Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models
have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds
initial support for the Cortex-M4 in the libopencm3 library.

By using two different ram areas (pc_ram and ps_ram) the user can
put the code in a RAM area bounded to the code bus. The data can
be stored in the data area. However, currently the initial values
of for the variables in the data section are stored in the code
section and copied to the ram section by the initialization code
(like it's copied from ROM to RAM on microcontrollers).
vf6xx: set vector table to memory

Set Vector Table Offset to memory location of our vector table.
Since we put the whole programm including the vector table into
memory, we need to make use of the Cortex-M4 system control block
Vector Table Offset Register (VTOR).
vf6xx: initial memorymap and clock control module

Add initial memorymap for Vybrid VF6xx module. Also add the clock
control module which allows to control system clocks and enable
clocks of individual pheripherials.
vf6xx: doc: initial commit

Add documentation Makefile and DoxygenLayout for Freescale Vybrid
VF6xx support.
vf6xx: enable floating-point coprocessor
vf6xx: calculate core clocks

Extend the clock controller module with a function to calculate
core clocks from the current registers settings. On Vybrid, we
assume that the core clocks are setup by the main operating system
running on the Cortex-A5. Nevertheless we need to know their actual
values in order to calculate other clocks or baud rates.

Verified on a Colibri VF61, which calculates following values:
ccm_core_clk: 500210526
ccm_platform_bus_clk: 166736842
ccm_ipg_bus_clk: 83368421
vf6xx: add UART support

This adds UART support for Vybrid VF6xx. Baud rate is calculated
from IPG clock, which need to be initialized by using the
ccm_calculate_clocks functions. Also clock need to be gated using
the ccm_clock_gate_enable function. Tested with an unitialized
UART with a baud rate of 115200.
vf6xx: initial GPIO support

This adds GPIO module support. GPIO can be controlled using the GPIO
number as stated in the reference manual, similar to Linux. Also
32-bit access to whole ports is possible. Reading a GPIO is possible
without muxing the pad as GPIO, however writing a GPIO needs the pad
to be muxed as GPIO.
vf6xx: add I/O mux controller

Add I/O mux controller which is required to mux pins according to
their used function. For all pads, the alternative function 0 is
GPIO. For different pin mux function refer to the reference manual.
[stm32l0] Initial support for STM32L0 architecture, Add GPIO peripheral
[stm32l0] Integrate the L0 architecture to the doxygen documentation

Conflicts:
	doc/Makefile
[Doxygen] Strip out architectures from Makefile dependencies

This commit shrinks the Makefile of the doxygen and makes easy error-prone addition of the new supported platforms.
The user should modify only one line at start of file to add new supported family to the build process.

The calling format is preserved and is compatible with old version of the makefile.
Update README with recently added targets
lpc17xx: trivial: fix description in linker script.
lpc17xx: memorymap: Fix AHB address and add peripherals
lpc17xx: memorymap: Add GPIO block at correct location