Assert that ValueHandleBase::ValueIsRAUWd doesn't change the tracked Value type.

This invariant is enforced in Value::replaceAllUsesWith, thus it seems
logical to apply it also to ValueHandles. This commit fixes InstCombine
to not trigger the assertion during the removal of constant bitcasts in
call instructions.

Differential Revision: http://reviews.llvm.org/D5828

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220468 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM, stack protector] If supported, use armv7 instructions.

This commit enables using movt/movw to load the stack guard address:

movw r0, :lower16:(L_g3$non_lazy_ptr-(LPC0_0+8))
movt r0, :upper16:(L_g3$non_lazy_ptr-(LPC0_0+8))
ldr r0, [pc, r0]

Previously a pc-relative load was emitted:

ldr r0, LCPI0_0
ldr r0, [pc, r0]

rdar://problem/18740489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220470 91177308-0d34-0410-b5e6-96231b3b80d8
[Thumb2] Improve disassembly of memory hints

Currently, the ARM disassembler will disassemble the Thumb2 memory hint
instructions (PLD, PLDW and PLI), even for targets which do not have
these instructions. This patch adds the required checks to the
disassmebler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220472 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D5774


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220474 91177308-0d34-0410-b5e6-96231b3b80d8
ps][microMIPS] Implement LI16 instruction
Differential Revision: http://reviews.llvm.org/D5149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220475 91177308-0d34-0410-b5e6-96231b3b80d8
ps][microMIPS] Implement ADDIUR2 instruction
Differential Revision: http://reviews.llvm.org/D5151


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220476 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement ADDIUR1SP instruction
Differential Revision: http://reviews.llvm.org/D5153


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220477 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r220427, "[Hexagon] Adding encoding bits for add opcode."

It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220478 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Prune trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220479 91177308-0d34-0410-b5e6-96231b3b80d8
[CMake] Prune CRLF in CMakeLists.txt(s).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220480 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon/LLVMBuild.txt: Prune CRLF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220481 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon/Disassembler/LLVMBuild.txt: Update libdeps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220482 91177308-0d34-0410-b5e6-96231b3b80d8
Add unittest for extreme alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220483 91177308-0d34-0410-b5e6-96231b3b80d8
clang-format two code snippets to make the next patch easy to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220484 91177308-0d34-0410-b5e6-96231b3b80d8
Do not emit intermediate register for zero FP immediate

This updates check for double precision zero floating point constant to allow
use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

vmov.i32        d16, #0x0
vcmpe.f64       d0, d16

With this change it becomes:

vcmpe.f64        d0, #0

Patch by Sergey Dmitrouk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220486 91177308-0d34-0410-b5e6-96231b3b80d8
Remove explicit (void) use of DwarfFile::DD that was accidentally left in r220452.

Caught in post-commit review by Frédéric.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220487 91177308-0d34-0410-b5e6-96231b3b80d8
Adding llvm-shlib to CMake build system with a few new bells and whistles

Summary:
This patch adds a new CMake build setting LLVM_BUILD_LLVM_DYLIB, which defaults to OFF. When set to ON, this will generate a shared library containing most of LLVM. The contents of the shared library can be overriden by specifying LLVM_DYLIB_COMPONENTS. LLVM_DYLIB_COMPONENTS can be set to a semi-colon delimited list of any LLVM components that you llvm-config can resolve.

On Windows, unless you are using Cygwin, you must specify an explicit symbol export file using LLVM_EXPORTED_SYMBOL_FILE. On Cygwin and all unix-like platforms if you do not specify LLVM_EXPORTED_SYMBOL_FILE, an export file containing only the LLVM C API will be auto-generated from the list of LLVM components specified in LLVM_DYLIB_COMPONENTS.

Reviewers: rnk

Reviewed By: rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D5890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220490 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Don't count inreg params when mangling fastcall functions"

This reverts commit r214981.

I'm not sure what I was thinking when I wrote this. Testing with MSVC
shows that this function is mangled to '@f@8':
  int __fastcall f(int a, int b);

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220492 91177308-0d34-0410-b5e6-96231b3b80d8
Make this test a bit stricter.

This now:
* Forces the linker to include the internal definition.
* Checks the full output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220494 91177308-0d34-0410-b5e6-96231b3b80d8
Make this test a bit stricter.

This now:
* Forces the linker to include the internal definition.
* Checks the full output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220495 91177308-0d34-0410-b5e6-96231b3b80d8