FROMLIST: Documentation: arm: define DT idle states bindings

ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.

Therefore, this patch aims at standardizing idle state device tree bindings
for ARM platforms. Bindings define idle state parameters inclusive of entry
methods and state latencies, to allow operating systems to retrieve the
configuration entries from the device tree and initialize the related power
management drivers, paving the way for common code in the kernel to deal with
idle states and removing the need for static data in current and previous
kernel versions.

ARM64 platforms require the DT to define an entry-method property
for idle states.

On system implementing PSCI as an enable-method to enter low-power
states the PSCI CPU suspend method requires the power_state parameter to
be passed to the PSCI CPU suspend function.

This parameter is specific to a power state and platform specific,
therefore must be provided by firmware to the OS in order to enable
proper call sequence.

Thus, this patch also adds a property in the PSCI bindings that
describes how the PSCI CPU suspend power_state parameter should be
defined in DT in all device nodes that rely on PSCI CPU suspend method usage.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Sebastian Capella <sebcape@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
drivers: cpuidle: implement DT based idle states infrastructure

On most common ARM systems, the low-power states a CPU can be put into are
not discoverable in HW and require device tree bindings to describe
power down suspend operations and idle states parameters.

In order to enable DT based idle states and configure idle drivers, this
patch implements the bulk infrastructure required to parse the device tree
idle states bindings and initialize the corresponding CPUidle driver states
data.

The parsing API accepts a start index that defines the first idle state
that should be initialized by the parsing code in order to give new and
legacy driver flexibility over which states should be parsed using the
new DT mechanism.

The idle states node(s) is obtained from the phandle list of the first cpu
in the driver cpumask;  the kernel checks that the idle state node phandle
is the same for all CPUs in the driver cpumask before declaring the idle state
as valid and start parsing its content.

The idle state enter function pointer is initialized through DT match
structures passed in by the CPUidle driver, so that ARM legacy code can
cope with platform specific idle entry method based on compatible
string matching and the code used to initialize the enter function pointer
can be moved to the DT generic layer.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
FROMLIST: drivers: cpuidle: initialize big.LITTLE driver through DT

With the introduction of DT based idle states, CPUidle drivers for ARM
can now initialize idle states data through properties in the device tree.

This patch adds code to the big.LITTLE CPUidle driver to dynamically
initialize idle states data through the updated device tree source file.

Cc: Chander Kashyap <k.chander@samsung.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
msm: scm: Fix incorrect cache invalidation

The cache invalidation in scm_call() correctly rounds down the
start address to invalidate the beginning of the cacheline but
doesn't properly round up the 'end' address to make it aligned.
The last chunk of the buffer won't be invalidated when 'end' is
not cacheline size aligned so make sure to invalidate the last
few bytes in such situations. It also doesn't do anything about
outer caches so make sure to invalidate and flush those as well.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Get cacheline size from CTR

Instead of hardcoding the cacheline size as 32, get the cacheline
size from the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Flush the command buffer only instead of the entire cache

scm_call flushes the entire cache before calling into the
secure world. This is both a performance penalty as well
as insufficient on SMP systems where the CPUs possess a
write-back L1 cache. Flush only the command and response
buffers instead, moving the responsibility of flushing any
other cached buffer (being passed to the secure world) to
callers.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Add atomic SCM APIs

The atomic SCM APIs are useful for commands that are guaranteed
by the secure side to be uninterruptable, atomic and SMP safe.
The calling convention use registers for passing parameters and
return values between the secure and non-secure side. Support
this interface with  scm_call_atomic[1-2]() functions
corresponding to the number of arguments passed.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Add API to query for service/command availability.

Some drivers may need to query the secure environment about the
availability of a particular service/command. Add support for
this.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[sboyd@codeaurora.org: Add some commit text]

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Add a feat version query API

Some users of SCM need to detect features and also detect if
those features have certain versions available. Add this API.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Add logging of actual return code from scm call

When an error occurs during an scm call the error returned is
remapped so we lose the original error code. This means that
when an error occurs we have no idea what actually failed within
the secure environment.

Add a logging statement that will log the actual error code from
scm call allowing us to easily determine what caused the error
to occur.

Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Move the scm driver to drivers/soc/qcom

Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
scm driver to drivers/soc/qcom and the scm header to
include/soc/qcom to support that removal.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msm: scm: Move scm-boot files to drivers/soc and include/soc

Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
msm: scm: Add SCM warmboot flags for quad core targets.

Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warmboot addresses for secondary cores.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
qcom: scm: scm_set_warm_boot_addr() to set the warmboot address

Set the warmboot address using an SCM call, only if the new address is
different than the old one.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
qcom: spm: Add Subsystem Power Manager driver

SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest of low power mode sequence and brings the core
out of low power mode.

The SPM has a set of control registers that configure the SPMs
individually based on the type of the core and the runtime conditions.
SPM is a finite state machine block to which a sequence is provided and
it interprets the bytes and executes them in sequence. Each low power
mode that the core can enter into is provided to the SPM as a sequence.

Configure the SPM to set the core (cpu or L2) into its low power mode,
the index of the first command in the sequence is set in the SPM_CTL
register. When the core executes ARM wfi instruction, it triggers the
SPM state machine to start executing from that index. The SPM state
machine waits until the interrupt occurs and starts executing the rest
of the sequence until it hits the end of the sequence. The end of the
sequence jumps the core out of its low power mode.

Add support for an idle driver to set up the SPM to place the core in
Standby or Standalone power collapse mode when the core is idle.

Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
Original tree available at -
git://codeaurora.org/quic/la/kernel/msm-3.10.git

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
arm: dts: qcom: Add power-controller device node for 8974 Krait CPUs

Each Krait CPU in the QCOM 8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
arm: dts: qcom: Add power-controller device node for 8084 Krait CPUs

Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
arm: dts: qcom: Update power-controller device node for 8064 Krait CPUs

Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
qcom: cpuidle: Add cpuidle driver for QCOM cpus

Add cpuidle driver interface to allow cpus to go into C-States. Use the
cpuidle DT interface, common across ARM architectures, to provide the
C-State information to the cpuidle framework.

Supported modes at this time are Standby and Standalone Power Collapse.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
arm: dts: qcom: Add idle states device nodes for 8974

Add allowable C-States for each cpu using the cpu-idle-states node.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>