hdl/*/wb_position_calc/wbgen/*: update wbgen files

 - Included registers for reading Monit. Amplitudes and
Monit. Position data.

 - Fix some fields with wrong "clock" description.

 - Fix some fiels with wrong "access_*" description
 	for MONOSTABLE type regsiters

 - Fix size of K* registers. Changed from 26 to 25 bits wide.

 - Regenerated files from wbgen2.
hdl/sim/regs/wb_pos_calc_regs.vh: update verilog constants
hdl/*/wb_position_calc/*_counters*: add error counter

Added error counters for various DSP signals
hdl/*/wb_position_calc/*_pkg.vhd: update DSP package

Added error counters modules to package
hdl/*/wb_position_calc/*: update top position_calc modules

 - Removed top interface error and configuration signals. They
 	are now accesible only through the Wishbone interface.

 - Added error counter modules

 - Output Monit. amplitude and Monit. position data to
 	Wishbone registers. They can be read through
	polling the registers, as change slowly and
	are used only to check tendencies and slowly
	changing variations.
hdl/modules/wb_position_calc/Manifest.py: update Manifest

Now, it includes the error counters modules
hdl/modules/dsp_cores_pkg.vhd: update top files interface

 - Updated top "position_calc" files interface

 - Moved SDB records to this file. They were located
	 on the bpm-sw repository. It makes more sense
	 to reference them here.
hdl/modules/*: change location of SDB structures again.
hdl/modules/wb_un_cross/*: update wbgen files

 - Change gain register to 16-bit

 - Change naming of wbgen files