msm: clock-8974: Reduce PLL lock time

Current PLL locking sequence is taking minimum time of 4.6 msec.
For command mode panels, PLL will be disabled on system idle
screen and enabled back on first update. Very first display update
after idle screen is taking long time due to PLL locking sequence.
We need to optimize PLL lock time for better user experience.

Change-Id: I1604d4544a3b33ed668ae6f36d19a876c2923e0c
Signed-off-by: Shalabh Jain <shalabhj@codeaurora.org>
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
config: b3-t4