Avoid extracting bits that don't exist

Code such as the following

  class test extends Module {
    val io = new Bundle {
      val data = UInt(INPUT, width = 256)
      val offset = UInt(INPUT, width = 10)
      val bit = UInt(OUTPUT, width = 1)
    }

    io.bit := io.data(io.offset)
  }

is capable of extracting bits that don't exist from a wire.  This
translates into an array access in C++ after multi-word expansion
which in this case results in an out-of-bounds access, whic can SEGV.

This patch works around the problem by extending the input to the
nearest power of two and then computing the shift modulo that power of
two.  This eliminates the undefined behavior in C++ but appears to not
match Verilog (which I think specifies these bits read as 0), which is
a bit hairy.

Note that this happens entirely within chisel, essentially relying on
the backends to optimize this away.

This fixes bug #174
Work around a left-shift code gen issue

I don't really understand what's going on here, but this appears to
work around a code gen issue that chisel-torture found a while ago.
It appears that for some reason wordMangle() doesn't do the right
thing when running in non-debug mode, so I just went ahead and worked
around the problem.

I'm pretty sure this is the wrong solution, but I have no idea what
the correct one is.

This fixes chisel bug #239
Merge pull request #242 from palmer-dabbelt/too_many_bits

Avoid extracting bits that don't exist
Merge pull request #243 from palmer-dabbelt/left_shift_c++

Work around a left-shift code gen issue
Merge branch 'master' into wirewidthtypearithnamedparams

Conflicts:
	src/main/scala/Op.scala
Revert "Work around a left-shift code gen issue"
Merge pull request #245 from ucb-bar/revert-243-left_shift_c++

Revert "Work around a left-shift code gen issue"
Merge branch 'master' into wirewidthtypearithnamedparams