Initial project directory for Spring 2011 EE412 Multicycle MIPS.
Verilog modules and MIPS ASM test code for a Multicycle CPU. This is the solutions for Exercice 7.22.
Testing authentication
just testing the commit
Starting to add comments and change code to fit our style and competencies.
Replace test program with that from Example 7.12. This test is simpler. I verified that in ISE Simulator the simulation succeeds.
docx for project write up
ISE Simulator project files. Both might not be needed.
for lucas
Removing unused adder from single-cycle CPU. The one ALU is used for all arithmetic operations.
Lucas: adding generated files to svn:ignore list.
Lucas: removing states we are not implementing.
Adding cycle count to test bench. This will be used to add how many cycles the multicycle MIPS takes for the instructions. We will add the simulation waveform to the report and discuss expected results and compare it with a single cycle MIPS CPU.
Rename JUMP state and remove ORI, XORI states. Still have to remove the signals and bits used for these states (will wait for block diagram from Aaron.
Removed BNE, LBU states. Signals and hardware to be removed later.
fixed existing .doc
pictures for mips processor