drm/nouveau: support for probing platform devices

Add a platform driver for Nouveau devices declared using the device tree
or platform data. This driver currently supports GK20A on Tegra
platforms and is only compiled for these platforms if Nouveau is
enabled.

Nouveau will probe the chip type itself using the BOOT0 register, so all
this driver really needs to do is to make sure the module is powered and
its clocks active before calling nouveau_drm_platform_probe().

Heavily based on work done by Thierry Reding.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
ARM: tegra: of: add GK20A device tree binding

Add the device tree binding documentation for the GK20A GPU used in
Tegra K1 SoCs.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add GK20A GPU to Tegra124 DT

Add the GK20A device node to Tegra124's device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau/bar: add noncached ioremap property

Some BARs (like GK20A's) do not support being ioremapped write-combined.
Add a boolean property to the BAR structure and handle that case in the
Nouveau BO implementation.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/gk20a: add BAR instance

GK20A's BAR is functionally identical to NVC0's, but do not support
being ioremapped write-combined. Create a BAR instance for GK20A that
reflect that state.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/ttm: recognize ARM arch in ioprot handler

Nouveau can now be used on ARM, so add an ioprot handler for this
architecture.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau/vm: fix mapping of SG pages list

SG pages lists (not to be confused with scatterlists) are a list of 4KB
memory pages used to define a nouveau_mem. Mapping them to a VM that
does not use 4KB apertures resulted in each subsequent 4KB physical page
being mapped into a larger VM aperture, thus creating an incorrect,
overlapping mapping.

This patch fixes this issue by detecting when such mappings occur and by
skipping the required number of pages in the list to ensure a correct
linear mapping.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
ARM: tegra: venice2: enable GK20A GPU

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
ARM: tegra: jetson-tk1: enable GK20A GPU

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
[HACK] workaround to avoid FIFO regs freeze on T124

See bug 1417781
[DEBUG] Add channel dumping functions for NVEA
drm/gk20a/clock: initial implementation

Add support for changing the clock frequency on GK20A. Re-clocking is
currently only possible through a debugfs node, and none of the Nouveau
clock framework is effectively used due to its strong dependency on
BIOS. This patch thus only provides a temporary way of setting the GPU
clock to a decent frequency until something better is crafted.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
[HACK] prevent warnings during GK20A probe
[HACK] drm/nouveau/graph: do not write reg 0x260

What is it for anyway?
[HACK] add gk20a instmem

This is a gazillion times faster, but requires to invalidate the
GPU L2 (probably at a better place than this!)
drm/ttm: expose CPU address of DMA-allocated pages

Pages allocated using the DMA API have a coherent memory mapping. Make
this mapping visible to drivers so they can decide to use it instead of
creating their own redundant one.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: map pages using DMA API on platform devices

page_to_phys() is not the correct way to obtain the DMA address of a
buffer on a non-PCI system. Use the DMA API functions for this, which
are portable and will allow us to use other DMA API functions for
buffer synchronization.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: introduce nv_device_is_cpu_coherent()

Add a function allowing us to know whether a device is CPU-coherent,
i.e. accesses performed by the CPU on GPU-mapped buffers will
be immediately visible on the GPU side and vice-versa.

For now, a device is considered to be coherent if it uses the PCI bus on
a non-ARM architecture.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: synchronize BOs when required

On architectures for which access to GPU memory is non-coherent,
caches need to be flushed and invalidated explicitly when BO control
changes between CPU and GPU.

This patch adds buffer synchronization functions which invokes the
correct API (PCI or DMA) to ensure synchronization is effective.

Based on the TTM DMA cache helper patches by Lucas Stach.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
drm/nouveau: implement explicitly coherent BOs

Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which
means that we want the allocated BO to be perfectly coherent between the
CPU and GPU. This is useful on non-coherent architectures for which we
do not want to manually sync some rarely-accessed buffers: typically,
fences and pushbuffers.

A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent
architecture will be populated using the DMA API, and accesses to it
performed using the coherent mapping performed by dma_alloc_coherent().

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>