Adjust to vlang esdl.base.time getting moved to edsl.data.time.
Purge initRooutine function since it has been merged with initProcess in Vlang.
Added uvm_auto_build_phase to be run after uvm_build_phase.
Use template mixins for uvm_object_utils and uvm_component_utils.
Added Auto Build functionality.
UVM_AUTO iterate through the components width wise.
Fixed auto_build. Made testbench inst simpler.
Added parallelism context to uvm_components.
Make possible to add parallelism UDP to uvm_component instances.
Make uvm_compare work for all types that can be compared.
Renamed bvec as Bit and lvec as Logic.
Added ingress and egress FIFO ports for across root transactions.
Allow launching UVM simulation in bg.
Fixed inadvertent typo in comments.
Temp fix for setint. Not functional yet.
Use D style syntax for array declarations.
Added function for only elaborate a uvm testbench.
Enabled multicore specification at run-time.
Fixed randomization issues.
Merge pull request #17 from puneet/master

updates