target-mips: add Config5.FRE support

FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available.

Config5.FRE: Allows emulation of Status.FR=0 handling on a 64-bit FPU with
             Status.FR=1. When enabled all single-precision FP arithmetic
             instructions cause a Reserved Instructions exception.

Config5.UFE: Allows user to write Config5.FRE using CTC1, and Config5.FRE
             using CFC1.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>