cache: use per-block unique for-loop index variables

Icarus can't handle several different blocks that are using the
same for-loop index variable.
cappuccino/ctrl: set npc to pc_ctrl_i on trap stall

A stall caused by a trap instruction (sw breakpoint) should set
npc to the pc where the stall ocurred. Since the exception
signal goes high in ctrl/mem stage, the current pc is pc_ctrl_i.
cappuccino: add support to read gpr via spr

This adds an extra register file read port, for access to the
gpra via spr.
So far only read access.
The motivation for adding a complete seperate rf_ram is that
it's least intrusive and muxing the address port of one of
the 'real' rf_rams can be avoided.
The downside is of course that it's a bit of a resource waste.
add support for l.lwa/l.swa atomic instructions

This adds support for the l.lwa and l.swa atomic instructions
per the suggestion here:
https://www.dropbox.com/s/yqyfelu2yrutzwt/openrisc-arch-1.1-rev0.pdf

Currently only cappuccino makes use of them
cappuccino/fetch: deassert ibus_req on rst
bus_if_wb32: Don't access bus on reset

The strobe and cycle signal are masked with rst. This suppresses
invalid bus accesses while the core is reset when core and bus/slaves
have different reset signals.
Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). Furthermore it is possible to read the number of
processor cores in a cluster via register 129. Both can apparently not
be written.

The registers are set via ports, which allow easier use in verilated
models or similar.
Debug: Execution traceport

The execution traceport traces all executed program counters, the
respective instruction and accesses to the register file with this
instruction. A rudimentary set of trace actions can be implemented in
a synthesizable way.

Set FEATURE_TRACEPORT_EXEC="ENABLED" to enable this trace port.

Add monitor for simulation.
cappucino-ctrl: Add two ISRs in multicore mode

We need something like shadow registers in multicore mode as we need
to do clean calculations on exceptions. Add two ISRs (ISR0 and ISR1)
which are used as scratch registers on exceptions.

squashed Stefan's commit:

add some more writeable ISR regs

This should be sorted out.
I think the best way to get scratch regs would be to
make a hybrid of the fast context switching and allow
using sets of GPRs (i.e. set 1 for reg stash)
WIP: Add snoop port