Add "--testerSeed <N>" command-line argument

The Scala tester uses a random number generator that's currently not
seeded.  This leads to non-determinstic tester behavior, which can be
a pain when you're trying to debug something.

This patch adds a "--testerSeed N" command-line option to Chisel.
This sets the RNG's seed to N.  Without this option the old behavior
is retained.
get rom writing to work
use DREAMER env var for flo tester
Randomize more than 32 bits of disconnected inputs
Fix ROMs for Verilog synthesis

We were previously emitting syntactically incorrect Verilog.

I refactored the way ROMs are handled.  We no longer associate the ROM
type with data emission.  Since ROM inherits from Vec, there's just too
much baggage.  Instead, the data is now contained in a ROMData class,
and ROMRead treats ROMData as one of its inputs.  Thus, multiple ROM
ports share the same data store (unlike in previous Verilog output).
For multi-ported ROMs, this is potentially beneficial for C++/Flo/FPGA.
add int conversion methods to tester docs
Merge pull request #154 from palmer-dabbelt/random_seed2

Add "--testerSeed <N>" command-line argument
merge
add seed printing and failure cycle reporting to tester
fix Chisel's Printf doesn't detect Bundles in place of Bits -- bug 51
fix flo-dir for tester for flo
Order printf output for Verilog
Add test for Mem[Bundle]
Work around false assertion failures
merge master