opp4xxx_data.c:
remove setting and voltage data for 3rd gpu opp as we can only use 2 steps,why have 2+ 1 that does nothing?
l3 cache overlocking
match the sgx/pvr system configuration header to match the new gpu clock speed
ASoC: OMAP ABE: Update to release 09.56

Update ABE firmware to 09.56. This firmware has the
next update:
- Add MONO 16 bits support
- Update SRC 48->96 kHz.
- Enable 4/16/48 kHz on Voice port and BT.
- Enable DL1 path to Handsfree path
- Add new filter functions for DMIC

Change-Id: Idbc527887b8cbd97ea1882562763950c6144add2
Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com>
OMAP4: clock: Fixing clock internal source selection for ABE ports

ABE ports need a mask of two bits in order to select the
correct internal source clock. This patch fix this mask that
was only one bit and was overlaping with source clock bits.

Change-Id: I8597efd9cec6707e815da39598a0adb7a3ce3c61
Signed-off-by: Israel Cepeda <icepeda@ti.com>
OMAP4: DSS: Implement workaround for Errata ID:i733.

Description of Errata i733:
Due to wrong timings, all register accesses transitioning through the L4
interconnect toward DSS are not reliable.

Workaround:
DSS register access should be addressed through the L3 interconnect.

This change fixes errata by using L3 for access to DSS in dss_hwmod
instead of L4.

Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0

Change-Id: Ie087b861ee653a3beeacba74c3afe7b1a0490ed4
Co-author: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
OMAP4: EMIF: unify access to EMIF_PWR_MGMT_CTRL.REG_LP_MODE

Use set_lp_mode for changing EMIF_PWR_MGMT_CTRL.REG_LP_MODE.

Change-Id: Ia6410f97c8937faee6fbfc335d5d1158de41583b
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>