MIPS: add MIPS_L1_CACHE_SHIFT_2

Some older machines such as the DECStation use a L1 data-cache shift of
2 (value of 4), add a Kconfig symbol for this value so they can express
this requirement.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6395/
MIPS: fix DECStation build for L1_CACHE_SHIFT value

When support for the DECStation is enabled, it will default to use a
MIPS R3000 class processor. This will cause an intentional build failure
to popup because MIPS_L1_CACHE_SHIFT and cpu_dcache_line_size()
disagree. Fix this by selecting MIPS_L1_CACHE_SHIFT_2 when we build
targetting a MIPS R3000 CPU to fix that build failure and satisfy all
requirements.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6394/
fix for e47113b68d569dc371a37bd0c2247c2568a891b6