Adjust no inputs contract clk is reg nw with initial delay to be changed
fixed bug @ branch we should use the 30 least significant bits instead of the most in shifting operation
Merge branch 'Group_MIPS' of https://github.com/fakhreldin-m-abdelkhalik/Verilog-Mips into Group_MIPS
Merge pull request #14 from fakhreldin-m-abdelkhalik/Group_MIPS

Group mips