start ir branch
add variable name parsing for nodes and components
modified naming methods, placed before preElaborateTransforms. Seprated binding naming from other signal naming. And inclcued dfs in Module.scala
modified naming methods, placed before preElaborateTransforms. Seprated binding naming from other signal naming. And inclcued dfs in Module.scala
Merge branch 'ir' of https://github.com/ucb-bar/chisel into ir
modified nameIt hierarchy to give signal names before preElaborateTransforms and deal with type nodes. passed all tests except two
clean up
Merge branch 'master' of https://github.com/ucb-bar/chisel into ir
made nameSpace global
Merge branch 'master' of https://github.com/ucb-bar/chisel into ir
fixed Verilog clk domain outputs
defined nameIt for CompositeData
minor changes for naming
merge from master
merge master
Merge branch 'master' of https://github.com/ucb-bar/chisel into ir
merge master
pseudo-naming
add counters with target decoupling
Merge branch 'master' of github.com:ucb-bar/chisel into ir