cappuccino/decode_execute: fix copy-paste error

The execute_op_brcond_o signal should be cleared on a
decode_bubble_o, not forwarded the value from decode.
PIC: Make LEVEL triggered default

The EDGE triggered PIC behaves exactly like the architecture spec.
Unfortunately, or1200 legacy is the incorrect behavior. LEVEL is the
same on both and even the spec says that is the common way. Therefore
change the default of mor1kx.
Merge branch 'master' of github.com:wallento/mor1kx
cappuccino: remove execute_waiting_o/i from module interconnect

Since this signal is only used in ctr_cappuccino and is just the
negation of execute_valid, it makes more sense to generate the
signal internally in this module.
This also seperates the negated stall signals from ctrl stage
into an own public signal.
LSU: Fix bug with lwa and snoop of same address

When a snoop event occurs parallel to the lwa completion, the swa
should fail. This is enabled by this patch that essentially simply
changes the order of checking.
Merge branch 'master' of https://github.com/wallento/mor1kx
cappuccino/fetch: set ic_addr to pc_addr on du_restart_i

pc_addr will contain the du_restart_pc at this point.
cappuccino: fix debug unit "asynchronous" stall/resume

Stalling and resuming the CPU at arbitrary places hasn't worked
reliably.
This was especially noticable with the default profiling routines
in openocd, which works by sampling NPC when the cpu is stalled.
To fix this, some more distinctions between stalling when stepping
and stalling/resuming when not stepiing is needed.
Bump version number to 3.0
Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). Furthermore it is possible to read the number of
processor cores in a cluster via register 129. Both can apparently not
be written.

The registers are set via ports, which allow easier use in verilated
models or similar.
cappucino-ctrl: Add two ISRs in multicore mode

We need something like shadow registers in multicore mode as we need
to do clean calculations on exceptions. Add two ISRs (ISR0 and ISR1)
which are used as scratch registers on exceptions.
Debug: Execution traceport

The execution traceport traces all executed program counters, the
respective instruction and accesses to the register file with this
instruction. A rudimentary set of trace actions can be implemented in
a synthesizable way.

Set FEATURE_TRACEPORT_EXEC="ENABLED" to enable this trace port.

Add monitor for simulation.
WIP: Add snoop port
cappuccino/cpu: use execute_valid_o instead of !execute_waiting_o

execute_waiting_o have been removed since it was redundant.
add some more writeable ISR regs

This should be sorted out.
I think the best way to get scratch regs would be to
make a hybrid of the fast context switching and allow
using sets of GPRs (i.e. set 1 for reg stash)
Correct handling of FEATURE_MULTICORE