[Hexagon] Adding packhl instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223664 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify test. NFC.

This is just testing the largest merge mode for comdats. No need to use
hard to read names and fancy types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223665 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify the test. NFC.

Since the main file was empty, we can just copy the content of the Input file
into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223666 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding combine reg, reg with predicated forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223667 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] Improved tablegen patters for matching TZCNT/LZCNT.

Teach ISel how to match a TZCNT/LZCNT from a conditional move if the
condition code is X86_COND_NE.
Existing tablegen patterns only allowed to match TZCNT/LZCNT from a
X86cond with condition code equal to X86_COND_E. To avoid introducing
extra rules, I added an 'ImmLeaf' definition that checks if the
condition code is COND_E or COND_NE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223668 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: treat HFAs containing "half" types as blocks too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223669 91177308-0d34-0410-b5e6-96231b3b80d8