Fixes to Counter Machine

1. The clocking lines have been switched around on the PC to fix a bug
where INC or DEC isn't performed correctly

2. Added a MUX to do register select, this passes through the LSB of the
instruction IFF BIT 3 isn't set. If it is, we select R0 so that we get
the output of R0 and not R1 if the LSB of the instruction is set
Add another output register to the ALU to prevent weird jump errors