bsp/altera-cyclone-v: Change console baud rate

The baud rate of the altera cyclone-V U-Boot can not be changed at the
u-Boot console prompt. Thus we use the same baud rate as the U-Boot for
the BSP.
bsp/altera-cyclone-v: Cleanup
libchip: Improve handling of DMA suspends

Reset the corresponding DMA status bit
libchip: Cleanup
libchip: Reduce tx interrupts

Reduce number of packet transmitted interrupts by using the interrupt mechanism only
if we run out of DMA descriptors.
Under normal conditions regaining DMA descriptors, mbufs and clusters is handled
via a counter.
libchip: Correct error handling in dwmac driver

By fault an rtems_status_code has been expected instead of an errno error number.
bsp/arm: Cleanup L1 cache
bsp/arm: Correct detection of arm erratum 764368
bsp/arm: Erratum 764369 after enabling SCU

Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
bsp/arm: RTEMS_SMP to arm erratum 764369 detection

Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
bsp/arm: Consistenly same handling for flushing

It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
bsp/arm: Remove arm erratum 764369 from L2 cache

Arm erratum 764369 only applies to the level 1 cache.
bsp/arm: Correct L2 cache flushing

Correct misalignment handling and prepare for locking.
bsp/arm: Correct cache misalignment handling

Correct misalignment handling and prepare for locking.
bsp/arm: Remove unused cache store methods
bsp/arm: Add L2 cache locking

This level 2 cache is a shared data and instruction cache and thus needs locking.
bsp/arm: Add cache size methods

Add new methods which deliver the cache sizes of for supported cache levels.
bsp/arm: Correct L2 cache enable method
bsp/arm: Cleanup L2 cache handling