Add pin mapping spreadsheet and PDF for P8X32 Nano
Converting tabs in .tdf files to spaces
More fixes of messy tab->space conversions

I did this by running a full comparison with BeyondCompare between Heater's initial commit (a76f883e9bfd146345f39f2db43420a4cca49e70) and the latest version, and making sure that my files ONLY contained the bug fixes but NOT the tabulation/spacing changes.
Added P8X32A_Pipistrello
Merge pull request #1 from magnuskarlsson/master

Added P8X32A_Pipistrello
Thanks Magnus!
More tab->space conversions

Don't know what happened but some earlier changes got lost and had to be
redone. I'll figure out this Git thing eventually, I promise! :-)
Deleting and ignoring more Quartus-generated files
Allowing the character ROM for the BeMicro CV

For some reason the BeMicro CV compilation failed earlier until I
disabled the character ROM, but apparently it works fine (I have one
myself now so I can test ;-)
Reverted changes for Spartan3E compile
Merge pull request #2 from magnuskarlsson/master

Reverted changes for Spartan3E compile
Fixed BeMicro CV LEDs

Modified the order of the LEDs to match the order on the PCB, and
inverted them in the top.tdf file so they're ON when the cogs run, OFF
when they don't.
Add new variant for Digilent Nexys4 (Artix 7)

Remember to set Propeller tool to use RTS as the reset signal when using
the Nexys4 board. (There's no DTR in the built-in UART.)
Preparing for merge of Nexys4

Andrewsil1 created a new Xilinx target Nexys4, but it was based on an
earlier version of Magnus Karlsson's branch, which has since been
reverted. I merged Magnus' latest changes into Andy's tree, which also
replaced tabs by spaces.
Reconfigure to "stock" Propeller 1 memory map

Restored hub memory to original design, including 32K hub RAM, and full
ROMs including the math tables and Propeller font.  For more usable
memory, it's not hard to go back to the 4K ROM files and hub_mem.v
provided by the Pipistrello version, but I wanted to be able to have the
full functionality of the original chip.

Also:
1) Added a Xilinx-specific Clock-Enable primitive for the video clock
signals rather than the LUT-driven scheme.
2) Modified constraints to connect several IOs to the Nexys4 VGA port in
the same fashion as the Propeller Demo Board, and verified that video
output applications behave correctly.
Modified Xilinx Project file for Nexys4

This file needs to reference the Nexys4 constraints UCF file and
eliminate the Pipistrello reference in order to compile properly.
Final recompiled bitfile

For "Stock" propeller emulation on Artix7/Nexys4 board, including video
output wired as per the Propeller Demo Board.
Merge Andy's changes to Nexys4 directory
Fixed bug in simulated PLL

See http://forums.parallax.com/showthread.php/157387
Fixed bug in simulated PLL

See http://forums.parallax.com/showthread.php/157387
Fixed bug in simulated PLL (Nexys variant)

Adding the bugfix to the Nexys subdir as well.