Truncate the immediate in logical operation to the register width

And continue to produce an error if the 32 most significant bits are not all ones or zeros.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212520 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Refactor ARM subarchitecture parsing"

This reverts commit 7b4a6882467e7fef4516a0cbc418cbfce0fc6f6d.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212521 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums

Summary:
Follow on to r212519 to improve the encapsulation and limit the scope of the enums.

Also merged two very similar parser functions, fixed a bug where ASE's
were not being reported, and marked CPR1's as being 128-bit when MSA is
enabled.

Differential Revision: http://reviews.llvm.org/D4384


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212522 91177308-0d34-0410-b5e6-96231b3b80d8
Fix r212522 - [mips] Improve encapsulation of the .MIPS.abiflags implementation and limit scope of related enums

Added two lines that should have been in r212522.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212523 91177308-0d34-0410-b5e6-96231b3b80d8