Merge pull request #1 from m-liu/master

Connected flash model with strStr. Compiles BSIM, untested
changed flat.py to pcieflat (to match installed name)
parse '-j <jsonfilename>' parameter to pcieflat
implemented '-j <interfacemap> <jsonfile>' option for pcieflat
removing obsolete files
updating names in algo2_nandsim
Merge branch 'master' of https://github.com/cambridgehackers/connectal
oops, commited extra file