Interpreter: fix carry calculation in srawx

I don't know anything this affected, but it didn't match the manual (or JIT).
JIT: some paired singles optimizations
JIT: various float optimizations
JIT: Various JitAsmCommon optimizations

Use some SSE4 instructions in on CPUs that support them.
Use float instructions instead of int where appropriate (it's a cycle faster
on CPUs with arithmetic unit forwarding penalties).
JIT: add fselx implementation

Based on a patch by Tilka.
DolphinQt: initial commit.

This adds the beginning of the DolphinQt user interface. It doesn't
do anything useful yet and only builds via CMake.
Qt: Add msvc support
Add Qt submodule for windows.
GekkoDisassembler: fix some float opcodes
Add hotkeys to select save state slots and to save/load the currently selected slots.
Merge pull request #1094 from FioraAeterna/fixdisasm2

GekkoDisassembler: fix some float opcodes
Merge pull request #686 from FioraAeterna/fiora

JIT: Optimize JitAsmCommon, Float, and PS implementations
Merge pull request #1090 from shuffle2/dolphin-qt

DolphinQt -- initial commit
JIT: use cvtsi2ss in paired singles

One less instruction for a few of the loads.
JIT: update some rather outdated comments
Merge pull request #1099 from FioraAeterna/updatecomments

JIT: update some rather outdated comments
JIT: simpler fallback conditions for load/store float

I wasn't really thinking when I wrote these; d/s are for float registers, not
gprs.
Wrap some function calls in ABI_Push|PopRegistersAndAdjustStack(0, 0);

These calls are made outside of JIT blocks, and thus previously did not
read any protection - register use is taken into account and the outer
dispatcher stack frame is sufficient.  However, if data is to be stored
on the stack, these calls must reserve stack shadow space on Windows to
avoid clobbering it.
Opportunistically predict BLR destinations using RET.

When executing a BL-type instruction, push the new LR onto the stack,
then CALL the dispatcher or linked block rather than JMPing to it.  When
executing BLR, compare [rsp+8] to LR, and RET if it's right, which it
usually will be unless the thread was switched out.  If it's not right,
reset RSP to avoid overflow.

This both saves a trip through the dispatcher and improves branch
prediction.

There is a small possibility of stack overflow anyway, which should
be handled... *yawn*
Shorten the blr stub a bit.