fix reading of high byte for jsr/bsr destination.
work on PH? and PL? instructions.
write registers in same cycle for single cycle operations.
adjust some comments.
try to track down source of delayed register writes.
make dual-port rams run at cpuclock to minimise memory read
waitstates. keep registers at 32mhz however for now.
fix instruction prefetch PC increment (or lack thereof) bug.
tweak IO waitstates to work on the assumption that all dual-port
buffer memories will be clocked at cpuclock and all other io registers
will be at IO clock.  This means we can eventually reduce waitstates
down to 1.