First thing in reorganization: moving files around.

Next step: get it to compile.
Change module names; simulator compiles!
Make everything related to hardware synthesis compile + TODO updated.
Change behavior of zero and one (do not create a new wire for every 0).
Found a very small example which our netlist generation can't handle.
Small change.
Fix problems with laziness by adding static info.
Actual commit to fix problems with laziness (ignore previous).
Delete the useless 'minijazz' folder.
Modify README and TODO.
Slight changes to README.
Give names to ROM chips so they can be initialized.
Start of DisplayClock.hs.
Displaying integers to the screen!
Code cleanup to prepare for the incoming changes.
Decide on a choice of concurrency primitives.
Synchronization successful!
Fix version number and add SDL dependency.
Simulation in clock mode works!
Aesthetic enhancements to the 7-segments display.