Elaborate root tasks/functions.
Get $root scope tasks/fuctions down to the ivl_target API.
Merge branch 'master' of github.com:steveicarus/iverilog
Merge pull request #45 from orsonmmz/subprogram

Subprograms
Handle functions in $root scope.
Fix parse.y bad handling of file names in some situations.

The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.

Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
vhdlpp: Support for 'left & 'right attributes.
vhdlpp: Added ExpAttribute::write_to_stream().
vhdlpp: prange_t may have the direction determined automatically.
vhdlpp: Support for 'range and 'reverse_range attributes.
vhdlpp: Skip signed & unsigned in types dump in packages.
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
vhdlpp: Fix array typedefs in packages.
vvp: Accepts continuous assignment for 2-state nets.
vhdlpp: Evaluation for 'left and 'right attributes.
vhdlpp: Smarter determining the direction in for loops.