Attempt to placate compilers that warn on casts between pointer-to-object and
pointer-to-function types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209490 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209495 91177308-0d34-0410-b5e6-96231b3b80d8
MC: remove unnecessary restriction on tests

Rafael correctly pointed out that the restriction is unnecessary.  Although the
tests are intended to ensure that we dont abort due to an assertion, running the
tests in all modes is better since it also ensures that we dont crash without
assertions.  Always run these tests to ensure that we can handle invalid input
correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209496 91177308-0d34-0410-b5e6-96231b3b80d8
DebugInfo: Fix cross-CU references for scopes (and variables within those scopes) in abstract definitions of cross-CU inlined functions

Found by Adrian Prantl during post-commit review of r209335.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209498 91177308-0d34-0410-b5e6-96231b3b80d8
Rename a couple of variables to be more accurate.

It's not really a "ScopeDIE", as such - it's the abstract function
definition's DIE. And we usually use "SP" for subprograms, rather than
"Sub".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209499 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-ar: Output the file we errored on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209500 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit.

The keyword "virtual" is not necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209501 91177308-0d34-0410-b5e6-96231b3b80d8
Typedef NumeredTypesMapTy is not used anywhere.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209502 91177308-0d34-0410-b5e6-96231b3b80d8
[YAML] Add an optional argument `EnumMask` to the `yaml::IO::bitSetCase()`.

Some bit-set fields used in ELF file headers in fact contain two parts.
The first one is a regular bit-field. The second one is an enumeraion.
For example ELF header `e_flags` for MIPS target might contain the
following values:

Bit-set values:

  EF_MIPS_NOREORDER = 0x00000001
  EF_MIPS_PIC       = 0x00000002
  EF_MIPS_CPIC      = 0x00000004
  EF_MIPS_ABI2      = 0x00000020

Enumeration:

  EF_MIPS_ARCH_32   = 0x50000000
  EF_MIPS_ARCH_64   = 0x60000000
  EF_MIPS_ARCH_32R2 = 0x70000000
  EF_MIPS_ARCH_64R2 = 0x80000000

For printing bit-sets we use the `yaml::IO::bitSetCase()`. It does not
support bit-set/enumeration combinations and prints too many flags from
an enumeration part. This patch fixes this problem. New method
`yaml::IO::maskedBitSetCase()` handle "enumeration" part of bitset
defined by provided mask.

Patch reviewed by Nick Kledzik and Sean Silva.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209504 91177308-0d34-0410-b5e6-96231b3b80d8
Fixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel headers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209506 91177308-0d34-0410-b5e6-96231b3b80d8
Updated the llvm.mem.parallel_loop_access semantics to include the possibility
to have only some of the loop's memory instructions be annotated and still _help_
the loop carried dependence analysis. 

This was discussed in the llvmdev ML (topic: "parallel loop metadata question").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209507 91177308-0d34-0410-b5e6-96231b3b80d8
[asan] properly instrument memory accesses that have small alignment (smaller than min(8,size)) by making two checks instead of one. This may slowdown some cases, e.g. long long on 32-bit or wide loads produced after loop unrolling. The benefit is higher sencitivity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209508 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6

Summary:
Instead the system is required to provide some means of handling unaligned
load/store without special instructions. Options include full hardware
support, full trap-and-emulate, and hybrids such as hardware support within
a cache line and trap-and-emulate for multi-line accesses.

MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to
assume that unaligned accesses are 'fast' on the basis that I expect few
hardware implementations will opt for pure-software handling of unaligned
accesses. The ones that do handle it purely in software can override this.

mips64-load-store-left-right.ll has been merged into load-store-left-right.ll

The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has
been fixed and the variables renamed to clarify the units they hold.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209512 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6/MIPS64r6

Summary: Depends on D3872

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3891

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209513 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Work around inconsistency in llvm-mc's placement of fixup markers

Summary:
Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly
position llvm-mc's fixup placeholders for big-endian.

See PR19836 for full details of the issue. To summarize, the fixup placeholders
do not account for endianness properly and the implementations of
getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset
from different ends of the instruction encoding to compensate.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3889

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209514 91177308-0d34-0410-b5e6-96231b3b80d8
WIP: Initial attempt at symbol_offset

Don't know how to produce assembler for this however.