rework the pll clock to mirror the actual hardware better

The included muxing in the previous version felt artificial and also
did not take the second xin32k source into account at all.
Now we create two stacked clocks one for the actual pll and on top
of it the mux-clock for handling the source selection for the actual
pll output.
dts: set the clock-output-name for the hym8563 clock to xin32k
as required by the core clock controller
rtc: hym8563: add optional clock-output-names property

This enables the setting of a custom clock name for the clock provided by
the hym8563 rtc.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>