ARM: zImage: ensure it is always a multiple of 64 bits in size

This is needed for proper alignment when the DTB appending feature
is used.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I18dd4220a40984ab2551ca17a16db37193ffe80c
Original: 72bf0bce411d9df0935eb77256604212de8f89cc
Reviewed-on: http://git-master/r/108696
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: zImage: Allow the appending of a device tree binary

This patch provides the ability to boot using a device tree that is appended
to the raw binary zImage (e.g. cat zImage <filename>.dtb > zImage_w_dtb).

Signed-off-by: John Bonesio <bones@secretlab.ca>
[nico: ported to latest zImage changes plus additional cleanups/improvements]
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I93c54694a59b357eb550587b94c986dcb19ab954
Original: e2a6a3aafa9862c4a4b59f2a59b8f923d64a680e
Reviewed-on: http://git-master/r/107422
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: zImage: make sure appended DTB doesn't get overwritten by kernel .bss

The appended DTB gets relocated with the decompressor code to get out
of the way of the decompressed kernel.  However the kernel's .bss section
may be larger than the relocated code and data, and then the DTB gets
overwritten.  Let's make sure the relocation takes care of moving zImage
far enough so no such conflict with .bss occurs.

Thanks to Tony Lindgren <tony@atomide.com> for figuring out this issue.

While at it, let's clean up the code a bit so that the wont_overwrite
symbol is used while determining if a conflict exists, making the above
change more precise as well as eliminating some ARM/THUMB alternates.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I1590dcbb9789f20d4c56a1e1f7c40177acaa8a2d
Original: 5ffb04f6690d71fab241b3562ebf52b893ac4ff1
Reviewed-on: http://git-master/r/107767
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: zImage: allow supplementing appended DTB with traditional ATAG data

Some old bootloaders can't be updated to a device tree capable one,
yet they provide ATAGs with memory configuration, the ramdisk address,
the kernel cmdline string, etc.  To allow a device tree enabled
kernel to be used with such bootloaders, it is necessary to convert those
ATAGs into FDT properties and fold them into the DTB appended to zImage.

Currently the following ATAGs are converted:

	ATAG_CMDLINE
	ATAG_MEM
	ATAG_INITRD2

If the corresponding information already exists in the appended DTB, it
is replaced, otherwise the required node is created to hold it.

The code looks for ATAGs at the location pointed by the value of r2 upon
entry into the zImage code.  If no ATAGs are found there, an attempt at
finding ATAGs at the typical 0x100 offset from start of RAM is made.
Otherwise the DTB is left unchanged.

Thisstarted from an older patch from John Bonesio <bones@secretlab.ca>,
with contributions from David Brown <davidb@codeaurora.org>.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: Ifb96adf6976da0f518c9c2cdad6be85f94c8ad1c
Original: b90b9a38251e9c89c34179eccde57411ceb5f1aa
Reviewed-on: http://git-master/r/107423
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: zImage: gather some string functions into string.c

This is a small subset of string functions needed by commits to come.
Except for memcpy() which is unchanged from its original location, their
implementation is meant to be small, and -Os is enforced to prevent gcc
from doing pointless loop unrolling.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: Ib6fd21beb8ee8804e472fb4ff5eb1cbea2b8e877
Original: df4879fa2603fbf0804a80f9f146ef9023dd621f
Reviewed-on: http://git-master/r/107424
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: zImage: prevent constant copy+rebuild of lib1funcs.S

The rule to copy this file doesn't have to be forced.  However
lib1funcs.[So] have to be listed amongst the targets.

This prevents zImage from being recreated needlessly.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>

Change-Id: I0ad0d4564835837abf15f0c590e8452bfef1c3a7
Original: 63d15148b6058ab0037343390e8918503ed81968
Reviewed-on: http://git-master/r/108698
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: 7017/1: Use generic BUG() handler

ARM uses its own BUG() handler which makes its output slightly different
from other archtectures.

One of the problems is that the ARM implementation doesn't report the
function
with the BUG() in it, but always reports the PC being in __bug(). The
generic
implementation doesn't have this problem.

Currently we get something like:

kernel BUG at fs/proc/breakme.c:35!
Unable to handle kernel NULL pointer dereference at virtual address
00000000
...
PC is at __bug+0x20/0x2c

With this patch it displays:

kernel BUG at fs/proc/breakme.c:35!
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP
...
PC is at write_breakme+0xd0/0x1b4

This implementation uses an undefined instruction to implement BUG, and
sets up
a bug table containing the relevant information. Many versions of gcc do
not
support %c properly for ARM (inserting a # when they shouldn't) so we
work
around this using distasteful macro magic.

v1: Initial version to replace existing ARM BUG() implementation with
something
more similar to other architectures.

v2: Add Thumb support, remove backtrace whitespace output changes.
Change to
use macros instead of requiring the asm %d flag to work (thanks to
Dave Martin <dave.martin@linaro.org>)

v3: Remove old BUG() implementation in favor of this one.
Remove the Backtrace: message (will submit this separately).
Rebase to linux-2.6.git master.

v4: Allow BUGS in modules (these were not reported correctly in v3)
(thanks to Stephen Boyd <sboyd@codeaurora.org> for suggesting that.)
Remove __bug() as this is no longer needed.

v5: Add %progbits as the section flags.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 87e040b6456fd3416a1f6831c1eedaef5c0a94ff)

Change-Id: Ic7692288dff6e4a15c732eb030295bd196a87fb4
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/117356
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
(cherry picked from commit 6708ffd0b44f4d09d8fe745471641545655091fb)
Reviewed-on: http://git-master/r/119328
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
arm: tegra: Add ATAG_SERIAL parsing

Bug 973078

Change-Id: I2860402c887db414717ce313101dc09e8b327f99
Signed-off-by: Chinmay Kamat <ckamat@nvidia.com>
Reviewed-on: http://git-master/r/108699
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
ARM: cache-l2x0: fix L2 maintenance for R3P1_50

Do flush and clear by set/way instead of by-way by enabling
errata 727915 for pl310 revision R3P1_50.
By-way maintenance doesn't work with enabled lp2_in_idle on
Tegra3 platform using R3P1_50 revision of pl310.

Debug register access causes hang when
CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those
regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined.

bug 983964

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6
Reviewed-on: http://git-master/r/125153
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
tracing: Clock lock trace events

Add tracing for clock lock/unlock operations.

Bug 960307

Change-Id: Id5c2d8be25900bc701e5dcd73f87c068ab6e5894
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/122666
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: tegra: clocks: Frequency stats for SCLK/CBUS

This adds a frequency histogram of the frequencies that SCLK
and CBUS clocks go to over time. Stats are presented in the
debugfs at /d/clock_stats/cbus and /d/clock_stats/sclk only if
debugfs is enabled in config

Change-Id: Icae83329612958d8ed4318b2e10c487683d9d734
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/118380
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
arm: tegra: read board info from device tree

Read board_info data from device tree instead of ATAGs,
if we're booting with device tree.

Bug 1001225

Change-Id: I2d659252a6a91f723bf4bb6c74918774650b87e2
Original-Author: Dan Willemsen <dwillemsen@nvidia.com>
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/116604
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: Tegra: Omit L2 flush at disable

In Tegra kernel L2 is disabled only upon CPU cluster power down,
e.g. LP2 entry. Flushing L2 upon every LP2 entry is costly.
Since we are always in single core mode upon cluster power down
we can safely omit L2 flush upon L2 disable.

Change-Id: I27542b11e6133f3192a02440e5b14ea408b860fd
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/105625
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
arm: tegra: display: provide framebuffer clear function

Add tegra_clear_framebuffer function.

bug 1175957

Change-Id: I12c249e011ecd839bbe9c5371b8be6e8a4b27bba
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/170661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arm: tegra: display: handle fbmem2 cmdline parameter

Parse and handle fbmem2 cmdline parameter.

bug 1175957

Change-Id: I0933825371bf13782e9f4364a4dba078929ae836
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/170662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
ARM: tegra: power: Trace LP2 entry and exit

Add traces for measuring LP2 entry/exit times.

Bug 960304

Change-Id: I20bb0f8d55a7ed6f7e88e10d924871a3d09f2507
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/123313
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: tegra: iovmm: Fix spinlock bug if alloc fails

iovmm_split_free_block leaves the domain's spinlock unlocked if a
memory allocation failed. Unfortunately, all the callers of that
function assume that it takes the spinlock. This will then lead to
double unlocking of the spinlock.

Bug 1035105

Change-Id: Ib4379cad76f053586d6a77b8d0dc9f41af01931a
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Reviewed-on: http://git-master/r/124299
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
ARM: tegra: enable errata 727915 for Tegra3

By-way maintenance doesn't reliably work with enabled
lp2_in_idle on Tegra3 platform which uses R3P1_50
revision of pl310.

Enable errata 727915 for Tegra3 to avoid system hang.

Change-Id: Ia296c1d5b35b8f28353c15d1e4622686bc7d3beb
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/127225
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
video: tegra: cardhu: Default bpp from hardware

This patch adds:

1. A kernel config option that hints to DC driver
to use the current value of the color depth
register as the default for initializing the FB
driver.

2. Checks to see if DC is enabled before reading
off the color depth register in tegra_dc_probe.

Change-Id: I852cc1328fcf42f33052f46b86d753e691744329
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Reviewed-on: http://git-master/r/127297
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: Set Core to 0.95V in LP1

When the device prepares for LP1, the Core voltage is set to the
highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and
Cardhu). This is to set for some of the driver suspend along the
sequence need a higher emc frequency and thus a higher Core voltage.

Since the sequence of drivers suspend depends on the sequence of
their registration in the table, which in turn is platform-dependent,
there is no right place in the LP1 entry path where the Core voltage
can be set to a lower voltage. Hence, the Core voltage remains high
in LP1 resulting in higher power.

Thus, the only safe location where the Core voltage can be lowered is
once all the drivers are suspended and the DRAM is set in self-refresh,
at the final point just before the system is suspended in the IRAM code.
This location at the assembly code ensures that no other module will be
running and thus that nothing will require a higher core voltage. The Core
is set to the lowest possible value since nothing requires it. It is then
restored to the highest voltage as soon as the LP1 resume code is started
so that all drivers are resumed safely.

At the execution point in IRAM during LP1 suspend path, even the I2C clocks
are gated. They must be reset first and then the I2C transaction is performed.
An I2C transaction involves 4 bytes of data, to send the slave address,
the Core voltage register address and 2 bytes of data which has the value
to set the voltage(the second byte is not required for this transaction).
Once these registers are set, the I2C transaction is performed by setting
the I2C transaction register to 0xA02. After sending the I2C transaction,
we wait for about 250us to check the status of the transaction and if not
updated, wait for more time to check again. If after 2ms and the transaction
fails to register, the transaction is aborted and the device is allowed
to enter at high voltage. Since the failure rate of I2C transaction is very
low at this point in execution where there will be no conflicts in the bus,
it is okay to have Core high for some of the LP1 cycles.

However, it is unacceptable for the I2C transaction to fail on the way
from LP1 resume since the device cannot come up with a lower Core
voltage. In this case, the transaction is retried again and again till
it is successful. There is no way but to keep trying as the device
would fail to resume with Core at 0.95V.

Each platform(or each PMU) has different values for the I2C transaction
ie. slave address, Core voltage register and the value to set the
voltage. For the device in IRAM, it cannot access anything in SDRAM
memory, these values needs to be pushed to IRAM memory before the device
starts execution in IRAM. This is done during initialization of suspend
code when it picks values from the board files and copies it to IRAM
part of code, before the whole memory is copied to IRAM.

This new feature is controlled by a KConfig variable TEGRA_LP1_950 which
should be enabled once the board file of the device is updated with the
right values. The device hangs when it does not have the right values for
the I2C transaction.

With this change in Core, LP1 power is reduced by 12mW in Enterprise,
20mW in AP37 and about 24mW in Kai.

Bug 1035684

Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/124135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>