ARM: sunxi: dt: list all pinctrl compatible strings

List all sunxi pinctrl compatible strings in order to be able to grep for
those values.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
ARM: sunxi: dt: document pinctrl clock related properties

Document clocks and clock-names properties for the pinctrl driver.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
ARM: sunxi: dt: add pinctrl clock-names properties

Add clock-names property to pinctrl node definitions.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk

Specify base pio clk name when retrieving it using the CCF.
This way we will avoid conflicts when introducing a second clk for the A31
SoC.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
clk: sunxi: add A31 APB0 clk gate defintions

Add APB0 gates support for the A31 SoC.
This gates are controlled by the PRCM (Power/Reset/Clock Management) block
and thus will act on a different iomem range.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
clk: sunxi: add A31 APB0 gates compatible string to the documentation

Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the
sunxi clock documentation.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
ARM: sunxi: dt: define A31's APB0 clk gates node

Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
Management) block.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
reset: sunxi: document sunxi's reset controllers bindings

Add DT bindings documentation for sunxi's reset controllers.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
clk: sunxi: add A31 APB0 reset line defintions

Add APB0 reset line support for the A31 SoC.
This reset lines are controlled by the PRCM (Power/Reset/Clock Management) block
and thus will act on a different iomem range.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
pinctrl: sunxi: add PL pin definitions

Define PL pin macros.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
pinctrl: sunxi: add support for A31 PL pins

The A31 SoC define a new memory region dedicated to PL pins.

Add a new get_membase callback to the sunxi_pinctrl struct in order to
retrieve the membase and relative pin number from an absolute pin number,
and make use of this new callback when manipulating the pins.

Currently, only the A31 SoC needs a specific conversion, the other one use
a contiguous memory region for all their pins.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC

Retrieve and enable the clock gate related to PL pins.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
pinctrl: sunxi: retrieve and enable PL reset line for A31 SoC

Retrieve and deassert the reset line related to PL pins.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
pinctrl: sunxi: define A31 PL0/PL1 pins

Define PL0/PL1 pins available on the A31 SoC.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
ARM: sunxi: dt: add support for A31's PL pins

The A31 SoC control its PL pins using a different memory, and needs both a
new gate clk and a reset line to enable these PL port.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
mfd: AXP20x: Add mfd driver for AXP20x PMIC

This patch introduces the preliminary support for PMICs X-Powers AXP202
and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit)
used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company
of Allwinner.

The core enables support for two subsystems:
- PEK (Power Enable Key)
- Regulators

Signed-off-by: Carlo Caione <carlo@caione.org>
dt-bindings: add vendor-prefix for X-Powers

Signed-off-by: Carlo Caione <carlo@caione.org>
mfd: AXP20x: Add bindings documentation

Bindings documentation for the AXP20x driver. In this file also
sub-nodes are documented.

Signed-off-by: Carlo Caione <carlo@caione.org>
input: misc: Add driver for AXP20x Power Enable Key

This patch add support for the Power Enable Key found on MFD AXP202 and
AXP209. Besides the basic support for the button, the driver adds two
entries in sysfs to configure the time delay for power on/off.

Signed-off-by: Carlo Caione <carlo@caione.org>
input: misc: Add ABI docs for AXP20x PEK

Add ABI entries for the PEK found on PMU X-Powers AXP202 and AXP209.

Signed-off-by: Carlo Caione <carlo@caione.org>