ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum

The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28

The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.

Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits about the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:29 and 29; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: rename OUT_CLK_SOURCE_*

OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: use MASK_BITS_* macros everywhere

Not all code that set or interpreted "mux_bits" was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.

Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.

Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: MASK_BITS_ no longer needs specific values

Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values, or interpret the values in
incorrect ways.

As such, remove the logic that assigns a specific value to the enum
values in order to make it completely clear that it's just an enum, not
something that directly represents some integer value.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: implement MASK_BITS_31_29

Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: amend pmc.h for Tegra114+

Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.

The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.

There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: don't exceed AVP limits when configuring PLLP

Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.

The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
[swarren, significantly refactored the changes, so that AVP only runs on
clk_m for the short duration that PLLP is being reconfigured. Fixed
Tegra30 too]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
LATER: ARM: tegra: add support for more clocks on Tegra114

FIXME: work on this later after Tegra124 support.
FIXME: re-write commit description now it's been split up...

Some Tegra114 peripherals can take up to 8 different clock sources
(parents), including 4 new ones that don't exist on previous chips
(PLLC2/C3/MEM2/SRC2). Expand clock/PLL code/tables to support these
additional bits/sources.

Changes were made to some common code. Testing on Tegra30 and Tegra20
showed no changes in periph clock sources/divisors.

Also, peripheral clock sources that no longer exist on Tegra114 were
removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs
that are gone or not needed in early init are no longer brought out of
reset/enabled (FUSE, IRAMA/B/C/D, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v3:
* Undid change to assert on divisor value; the fix was applied to the
  wrong assert. The assert which should have been fixed was within the
  removed unused code.
v2:
- Fixed an assert test for a divisor value (s/b >0, not >=0)
- Remove some unused code
Revert "LATER: ARM: tegra: add support for more clocks on Tegra114"

This reverts commit 6cf0329f447d51e1ad5909d46f79cfd4756a4c93.
LATER: ARM: tegra: dalmore: add PMIC init for various peripherals

FIXME: work on this later after Tegra124 support.

These power rails are currently needed for kernel boot. This will be move
to a PMIC-specific driver (or even better moved to the kernel) at a later
date.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Revert "LATER: ARM: tegra: dalmore: add PMIC init for various peripherals"

This reverts commit 2e5b746676e5360325456184750e979726b4a009.
ARM: tegra: add arch-tegra124 include/header files

No real HW change on Tegra124 for 90% of the toys, so just include
a common T1x4 header file (based on Tegra114 headers), and if a new
register/bit is needed, add it at the end. Some headers (clk_rst,
clock-tables, pinmux, etc.) had too many changes in structs,
devices, etc. added/removed, so they are added as complete new
files for Tegra124, and can be diffed against Tegra114 headers to see
what's changed (again, not a lot).

In a future (RSN) patch I'll point the Tegra114 headers at the
new common tegra1x4-xxx files, too.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Remove bogus unused prototype for board_usb_init().
ARM: tegra: support Tegra124 in common arch-tegra header files

Minor changes to support Tegra124 chip and sku IDs.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124

This provides SPL support for Tegra124 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles
* Update AVP/PLLP clock programming to match Tegra114
ARM: tegra: Add CPU (armv7) files for Tegra124

These files are for code that runs on the CPU (A15) on Tegra124 boards.
At this time, there is no A15-specific code here. The warmboot/LP0 files
aren't included as that code hasn't been ported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles
* s/MASK_BITS_29_28/MASK_BITS_31_28/ to match earlier renaming patch
* Update AVP/PLLP clock programming to match Tegra114
ARM: tegra: add common (shared) CPU files

These files are used by both SPL and main U-Boot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: Add generic Tegra124 build support

Basic Tegra124 build support added - no specific board is targeted.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add DT files for Tegra124 and Venice2

These are fairly complete, and near-clones of Tegra114 Venice, with an
additional I2C port, and MMC address changes for Tegra124.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: add Venice2 (Tegra124) board

These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC
files. PMIC init will be moved to pmic_common_init later.

This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display
and WB/LP0 are not supported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2:
* Convert to Kconfig-style make Makefiles
* Fix boards.cfg sort order
* Remove most functional diffs (i.e. other than SoC name, valid values,
  etc.) between include/configs/tegra1[12]4-common.h