Initial branch

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29034 3ad0048d-3df7-0310-abae-a5850022a9f2
Initial experimental support for GCRA.
tsubregister is used as the register class specifier.
The Squeeze function is not yet built into the system, and ra_resize reg allocs should probably be used.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29035 3ad0048d-3df7-0310-abae-a5850022a9f2
Branch for internal ARM writer based on patch from Anton in #26588.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29245 3ad0048d-3df7-0310-abae-a5850022a9f2
Add a lot of instruction table entries and missing instructions for support of most ARM32 mode instructions from ARMv4 up ARMv7A.
Add some VFP registers.
Rebuilt tables.
Added a lot of VFPv3 and Advanced SIMD(not supported yet) oppostfixes.
Implemented code in aasmcpu to generate binary code from the instructions. Only ARM32 supported so far.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29246 3ad0048d-3df7-0310-abae-a5850022a9f2
Implemented UAL syntax support in the ARM assembler reader. Can be toggled with a field for now, but not implemented yet. Still using pre-UAL syntax for now.
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29247 3ad0048d-3df7-0310-abae-a5850022a9f2
Fix some small encoding bugs.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29250 3ad0048d-3df7-0310-abae-a5850022a9f2
Small fix for uninitialized variables causing warnings.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29253 3ad0048d-3df7-0310-abae-a5850022a9f2
Encoding of preindexed LDRH/STRH opcodes was missing.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29254 3ad0048d-3df7-0310-abae-a5850022a9f2
Modify fixup of BL/BLX instructions and ensure proper form is generated.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29260 3ad0048d-3df7-0310-abae-a5850022a9f2
Forgot to rebuild instruction tables.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29261 3ad0048d-3df7-0310-abae-a5850022a9f2
Emitted instruction was B instead of BL for BL/BLX.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29262 3ad0048d-3df7-0310-abae-a5850022a9f2
Added some APSR register bitmask definitions.
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions.
Fixed emission of regsets of S and D registers above 15.
Fixed assembler reader for RRX shiftmode.
There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29277 3ad0048d-3df7-0310-abae-a5850022a9f2
Change emission of pre-reloc BLX to BL.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29278 3ad0048d-3df7-0310-abae-a5850022a9f2
Add a small function to handle encoding of CPU specific ELF flags. This is used to encode EABI version for ARM.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29281 3ad0048d-3df7-0310-abae-a5850022a9f2
 Make sure to change BLX instructions back to BL when the target is not a Thumb function.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29282 3ad0048d-3df7-0310-abae-a5850022a9f2
Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen).
Add missing fields to other elf targets.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29286 3ad0048d-3df7-0310-abae-a5850022a9f2
Fix capability matrix for ARMv5. It should not have thumb support.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29287 3ad0048d-3df7-0310-abae-a5850022a9f2
Added full 16-bit Thumb support to the ARM internal writer.

git-svn-id: http://svn.freepascal.org/svn/fpc/branches/laksen@29326 3ad0048d-3df7-0310-abae-a5850022a9f2