ARM: hw_breakpoint: *squashing updates*

ARM: hw_breakpoint: enable HAVE_HW_BREAKPOINT feature flag

      HAVE_HW_BREAKPOINT was disabled temporarily from commit
      480a82f59712136b51ee5ca05c4f22c1738010c5. Issue not seen with the
      latest kernel hence re-enable the feature and fix merge issue from
      previous kernel upgrade.

ARM/hw_breakpoint: upstream mainline

ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint access type

      From ARM debug architecture v7.1 onwards, a watchpoint exception causes
      the DFAR to be updated with the faulting data address. However, DFSR.WnR
      takes an UNKNOWN value and therefore cannot be used in general to
      determine the access type that triggered the watchpoint.

      This patch forbids watchpoints without an overflow handler from
      specifying a specific access type (load/store). Those with overflow
      handlers must be able to handle false positives potentially triggered by
      a watchpoint of a different access type on the same address. For
      SIGTRAP-based handlers (i.e. ptrace), this should have no impact.

ARM: 7497/1: hw_breakpoint: allow single-byte watchpoints on all addresses

      Breakpoint validation currently fails for single-byte watchpoints on
      addresses ending in 11b. There is no reason to forbid such a watchpoint,
      so extend the validation code to allow it.

ARM: hw_breakpoint: only clear OS lock when implemented on v7

      The OS save and restore register are optional in debug architecture v7,
      so check the status register before attempting to clear the OS lock.

ARM: hw_breakpoint: fix monitor mode detection with v7.1

      Detecting whether halting debug is enabled is no longer possible via
      the DBGDSCR in v7.1, returning an UNKNOWN value for the HDBGen bit via
      CP14 when the OS lock is clear.

      This patch removes the halting mode check and ensures that accesses to
      the internal and external views of the DBGDSCR are serialised with an
      instruction barrier.

ARM: hw_breakpoint: fix ordering of debug register reset sequence

      The debug register reset sequence for v7 and v7.1 is congruent with
      tap-dancing through a minefield.

      Rather than wait until we've blown ourselves to pieces, this patch
      instead checks the debug_err_mask after each potentially faulting
      operation. We also move the enabling of monitor_mode to the end of the
      sequence in order to prevent spurious debug events generated by UNKNOWN
      register values.

ARM: hw_breakpoint: don't try to clear v6 debug registers during boot

      v6 cores do not provide a way to clear the debug registers without first
      enabling monitor mode, meaning that we could take spurious debug
      exceptions. Instead, rely on the registers being in a sane state when we
      boot as they are defined to be disabled out of reset anyway.

ARM: hw_breakpoint: make boot quieter without CPUID feature registers

      Booting on a v6 core without the CPUID feature registers (e.g. 1136)
      leads to a noisy dmesg complaining about their absence.

      This patch changes the pr_warning into a pr_warn_once to keep the log
      quieter.

ARM: hw_breakpoint: check if monitor mode is enabled during validation

      Rather than attempt to enable monitor mode explicitly when scheduling in
      a breakpoint event (which could raise an undefined exception trap when
      accessing DBGDSCRext), instead check that DBGDSCRint.MDBGen is set
      during event validation and report an error to the caller if not.

ARM: hw_breakpoint: use CRn as argument for debug reg accessor macros

      The coprocessor register CRn for accesses to the debug register can be a
      different one than C0. Take this into account for the ARM_DBG_READ and
      the ARM_DBG_WRITE macro.

      The inline assembler calls which used a coprocessor register CRn other
      than C0 are replaced by the ARM_DBG_READ or ARM_DBG_WRITE macro.

ARM: hw_breakpoint: kill WARN_ONCE usage

      WARN_ONCE is a bit OTT for some of the simple failure cases encountered
      in hw_breakpoint, so use either pr_warning or pr_warn_once instead.

ARM: hw_breakpoint: Check function for OS Save and Restore mechanism

      v7 debug introduced OS Save and Restore mechanism. On a v7 debug SinglePower
      system, i.e a system without a separate core and debug power domain, which does
      not support external debug over powerdown, it is implementation defined whether
      OS Save and Restore is implemented.
      v7.1 debug requires OS Save and Restore mechanism. v6 debug and v6.1 debug do
      not implement it.

      A new global variable bool has_ossr is introduced and is determined in
      arch_hw_breakpoint_init() like debug_arch or the number of BRPs/WRPs.

      The logic how to check if OS Save and Restore is supported has changed with
      this patch. In reset_ctrl_regs() a mask consisting of OSLM[1] (OSLSR.3) and
      OSLM[0] (OSLSR.0) was used to check if the system supports OS Save and
      Restore. In the new function core_has_os_save_restore() only OSLM[0] is used.
      It is not necessary to check OSLM[1] too since it is v7.1 debug specific and
      v7.1 debug requires OS Save and Restore and thus OS Lock.

ARM: hw_breakpoint: Debug powerdown support for self-hosted debug

      This patch introduces debug powerdown support for self-hosted debug for v7
      and v7.1 debug architecture for a SinglePower system, i.e. a system without a
      separate core and debug power domain. On a SinglePower system the OS Lock is
      lost over a powerdown.

      If CONFIG_CPU_PM is set the new function pm_init() registers hw_breakpoint
      with CPU PM for a system supporting OS Save and Restore.

      Receiving a CPU PM EXIT notifier indicates that a single CPU has exited a low
      power state. A call to reset_ctrl_regs() is hooked into the CPU PM EXIT
      notifier chain. This function makes sure that the sticky power-down is clear
      (only v7 debug), the OS Double Lock is clear (only v7.1 debug) and it clears
      the OS Lock for v7 debug (for a system supporting OS Save and Restore) and
      v7.1 debug. Furthermore, it clears any vector-catch events and all
      breakpoint/watchpoint control/value registers for v7 and v7.1 debug.

ARM: 7662/1: hw_breakpoint: reset debug logic on secondary CPUs in s2ram resume

      We must mask out the CPU_TASKS_FROZEN bit so that reset_ctrl_regs is
      also called on a secondary CPU during s2ram resume, where only the boot
      CPU will receive the PM_EXIT notification.

ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs()

      CPU debug features like hardware break, watchpoints can be used only
      when the debug mode is enabled and available. Unfortunately on OMAP4
      based devices, after a CPU power cycle, the debug feature gets disabled
      which leads to a flood of messages coming from reset_ctrl_regs() which
      gets called on every CPU_PM_EXIT with CPUidle enabled.

      So make use of warn_once() so that system is usable.

      Thanks to Will for pointers and Lokesh for the analysis of the issue.

ARM: 7697/1: hw_breakpoint: do not use __cpuinitdata for dbg_cpu_pm_nb

      We must not declare dbg_cpu_pm_nb as __cpuinitdata as we need it after
      system initialization for Suspend and CPUIdle.

      This was done in commit 9a6eb310eaa5 ("ARM: hw_breakpoint: Debug powerdown
      support for self-hosted debug").

Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: moddingg33k <moddingg33k@t-online.de>