Updated 3500 PCIe SerDes config for Endpoint modes

Signed-off-by: SangeethaRao <sangeetha.rao@lsi.com>
board/lsi: Work Around for Reset Problem on 3500

Before a chip or system reset, switch the PPC clocks back
to the reference clock.  The errata is not yet available,
but here is a description of the problem.

The reset_system issue is caused since the 6 counters are
**NOT** reset by reset_system, but the PLL and clock switch
that controls the counters **IS**. Workaround for this:
switch clk_ppc to clk_ref before a reset_system or reset_chip.
This logically should work, BUT no STA work has been done to
validate this. Empirically, this seems to work.

Signed-off-by: John Jacques <john.jacques@lsi.com>