Fix bootstrap on powerpc64le-linux-gnu

2014-05-29  Tom de Vries  <tom@codesourcery.com>

	* final.c (collect_fn_hard_reg_usage): Guard variable declaration
	with #ifdef STACK_REGS.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211047 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/testsuite/
        * gcc.dg/vect/pr52252-ld.c: Fix target and options for the test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211048 138bc75d-0d04-0410-961f-82ee72b054a4
-fuse-caller-save - Enable for MIPS

2014-05-29  Radovan Obradovic  <robradovic@mips.com>
            Tom de Vries  <tom@codesourcery.com>

	* config/mips/mips.h (POST_CALL_TMP_REG): Define.
	* config/mips/mips.c (mips_emit_call_insn): Add POST_CALL_TMP_REG
	clobber.
	(mips_split_call): Use POST_CALL_TMP_REG.
	(TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS): Redefine to true.

	* gcc.target/mips/mips.exp: Add use-caller-save to -ffoo/-fno-foo
	options.
	* gcc.target/mips/fuse-caller-save.h: New include file.
	* gcc.target/mips/fuse-caller-save.c: New test.
	* gcc.target/mips/fuse-caller-save-mips16.c: Same.
	* gcc.target/mips/fuse-caller-save-micromips.c: Same.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211049 138bc75d-0d04-0410-961f-82ee72b054a4
        * arm/iterators.md (shiftable_ops): New code iterator.
        (t2_binop0, arith_shift_insn): New code attributes.
	* arm/predicates.md (shift_nomul_operator): New predicate.
        * arm/arm.md (insn_enabled): Delete.
        (enabled): Remove insn_enabled test.
        (*arith_shiftsi): Delete.  Replace with ...
        (*<arith_shift_insn>_multsi): ... new pattern.
	(*<arith_shift_insn>_shiftsi): ... new pattern.
	* config/arm/arm.c (arm_print_operand): Handle operand format 'b'.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211050 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-09  David Wohlferd <LimeGreenSocks@yahoo.com>
	Andrew Haley <aph@redhat.com>
	Richard Sandiford <rdsandiford@googlemail.com>

	* doc/extend.texi: Rewrite inline asm page / re-org asm-related
	pages.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211051 138bc75d-0d04-0410-961f-82ee72b054a4
	* include/tr2/bool_set: Use UTF-8 for accented characters.
	* scripts/run_doxygen: Handle Doxygen 1.8.x change.
	* doc/doxygen/user.cfg.in: Update to Doxygen 1.8.6 format. Set
	QUIET=YES, remove obsolete SYMBOL_CACHE_SIZE tag.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211053 138bc75d-0d04-0410-961f-82ee72b054a4
Fix rtl-check build

2014-05-29  Tom de Vries  <tom@codesourcery.com>

	* rtl.h (BLOCK_SYMBOL_CHECK): Use SYMBOL_REF_FLAGS.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211057 138bc75d-0d04-0410-961f-82ee72b054a4
Detect EXT patterns to vec_perm_const, use for EXT intrinsics

        * config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
        TYPES_BINOPV): New static data.
        * config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
        * config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
        New patterns.
        * config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
        patterns for EXT.
        (aarch64_evpc_ext): New function.

        * config/aarch64/iterators.md (UNSPEC_EXT): New enum element.

        * config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
        vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
        vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
        vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
        vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211058 138bc75d-0d04-0410-961f-82ee72b054a4
Add execution tests of ARM EXT intrinsics

	gcc.target/arm/simd/vextQf32_1.c: New file.
	gcc.target/arm/simd/vextQp16_1.c: New file.
	gcc.target/arm/simd/vextQp8_1.c: New file.
	gcc.target/arm/simd/vextQs16_1.c: New file.
	gcc.target/arm/simd/vextQs32_1.c: New file.
	gcc.target/arm/simd/vextQs64_1.c: New file.
	gcc.target/arm/simd/vextQs8_1.c: New file.
	gcc.target/arm/simd/vextQu16_1.c: New file.
	gcc.target/arm/simd/vextQu32_1.c: New file.
	gcc.target/arm/simd/vextQu64_1.c: New file.
	gcc.target/arm/simd/vextQu8_1.c: New file.
	gcc.target/arm/simd/vextQp64_1.c: New file.
	gcc.target/arm/simd/vextf32_1.c: New file.
	gcc.target/arm/simd/vextp16_1.c: New file.
	gcc.target/arm/simd/vextp8_1.c: New file.
	gcc.target/arm/simd/vexts16_1.c: New file.
	gcc.target/arm/simd/vexts32_1.c: New file.
	gcc.target/arm/simd/vexts64_1.c: New file.
	gcc.target/arm/simd/vexts8_1.c: New file.
	gcc.target/arm/simd/vextu16_1.c: New file.
	gcc.target/arm/simd/vextu32_1.c: New file.
	gcc.target/arm/simd/vextu64_1.c: New file.
	gcc.target/arm/simd/vextu8_1.c: New file.
	gcc.target/arm/simd/vextp64_1.c: New file.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211059 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-29  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/61325
	* lra-constraints.c (process_address): Rename to
	process_address_1.
	(process_address): New function.

2014-05-29  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/61325
	* gcc.target/aarch64/pr61325.c: New.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211061 138bc75d-0d04-0410-961f-82ee72b054a4