fexc: add some sanity checking to bin reading

Signed-off-by: Luc Verhaegen <libv@skynet.be>
meminfo: Initial upload
meminfo: do not assume Memory is always 24MHz * X

DDR runs from the PLL5 and has several option to be configured, just as
factor N, M, P and K. This patch probes all those registers to determine
the clock.
meminfo: swap PLL1 TUN2 register to proper location

PLL1_tun2 had a wrong comment (0x34) in the original and was swapped to
accomidate this position. Actually the comment was wrong and the
location right, so this patch puts pll1_tun2 to 0x38.
0x34 is now reserved.
meminfo: fix 'dram_tpr3' reporting

Get it from the dllcr registers instead of always returning 0.
meminfo: fix 'dram_clk' reporting for frequencies that are not multiples of 24

The K and M factors encode values 1-4 in two bits (starting from 1
and not 0). The typical DRAM clock frequency setup uses K=2 and M=2,
which means that both of them are read as 1 from the bit fields.
That's why a10-meminfo used to work in most cases (1/1 is the same
as 2/2). However a10-meminfo happens to report wrong 'dram_clk' if
the other values of K and M are selected. This patch fixes it.
meminfo: rename and add to build

* rename a10-meminfo to meminfo
* add static build to Makefile
* fix operand warning
* built binary verified on proper linux and android

Signed-off-by: Luc Verhaegen <libv@skynet.be>