arc: Workaround the possible issue with reading DDR memory

Similar to previous STAR, sometimes we read 0 instead of real memory
content, only this time it is a first read from memory, so we cannot add
artificial address writes. Instead now OpenOCD will check for JTAG status
register and will spin on this until it will set RD (ready) bit. In practice
it almost always set and I've never seen it not being set _before_ doing
memory read. So that is kind of a dummy useless check, since I haven't seen
cases where we would have to really wait for the JTAG interface. That
however seems to resolve the problem with failed reads, perhaps by adding a
delay between cache flush and memory read. Though that is quite strange
since in terms of the core time, there is already significant time between
flush and read.

Like with extra address writes this is applied only to "slow" memory (DDR)
and not to CCMs. It is also applied only to memory reads, though in theory
we should do this before each operations, that would add additional
performance penalty, and I don't feel inclined to decrease performance until
it will be obvious that it is required.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add an option to enable paranoia checks for JTAG status RD

Add an option "arc jtag always-check-status-rd on|off" that will force ARC
JTAG layer to check for RD bit of JTAG Status register. See already
existing code that does this before reading from DDR memory. This option is
off by default, since there are no known cases where this check is required
for anything else other than read from DDR memory.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: [trivial] Formatting of AUX register values in log

Use %08x instead of %x, so that presentation will be same as for core
registers

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add a warning when software breakpoint has been overwritten externally

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
arc: Add JTAG STATUS.FL checks after each operation

Check for FL bit in JTAG STATUS register and return error if this bit is
set, which usually indicates some kind of an error.

This however is disabled by default because it is known to break JTAG: there
is an undesired extra write after the indented one, so if we write, say,
DEBUG AUX register at 0x5, then we will also write same value to PC register
at 0x6, which is totally undesired.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>