msm: clock-krait: Clock ops library for Krait subsystem clocks

The Krait subsystem has its own clock tree. Implement a clock-krait library
that provides a set of clock ops that model all the clock components
present in the Krait subsystem clock tree.

Change-Id: I41bb4243c28cd666ebe8e7c5a814c85401d92308
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Fix register checking for div clock

Fix the wrong operand used to mask divider bits.

Change-Id: If2be61dece01b8171b31938b3d7c14fb497c0fd3
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-krait-8974: Run force reinit sequence for all CPUs

The HFPLL and krait mux force reinit sequence needs to be run for all CPUs
irrespective of whether they are online or offline. This is necessary to
ensure that when offline CPUs are brought online later on, they are brought
up at a known frequency.

To be able to do the above, we also have to remove the prepare count check
in krait core clock set rate ops. It's safe to do so since that check
wasn't really providing any additional protection on top of the checks
already done in the cpufreq driver.

Change-Id: Ia73459ee03d339c948d7f2ea9516df1c0d9b8bd0
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Always configure low performance level krait clock tree

With newer HW versions, switching between BHS and LDO power supplies also
switches the CPU between the high performance clock tree output and low
performance clock tree output respectively.

Since the low performance clock tree is never configured (since it was
never used before), with newer HW versions running the CPU off the LDO
supply would also run the CPU at an unknown frequency that could be higher
that the max frequency for that specific voltage/current level.

Fix this by always configuring the high performance clock tree and the low
performance clock tree to the same frequency. This change is also
compatible with HW versions that don't have a low performance clock tree
since the register bits that correspond to the low performance clock tree
are marked as unused/reserved.

Change-Id: Ie82bf735220619be7ffd496cbd8b017c89904b41
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Read CONFIG_CTL value and the vco mask from DT

The config control register may have different reset
values on different MSMs. Also, not all HFPLLS may need
to switch between VCO modes. Read both the config control
register initialization value and the VCO user control
mask from device tree.

Change-Id: I832ee3acaa7f4b7b0637d0732ddf275d9475e8bc
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
clock-krait-8974: Increase PVS bin efuse field to a 4-bit field

This also needs changes to the redundant fuse data field to support making
corrections to a 4-bit field.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Change-Id: Ia15e5375537ff587a502fae975fdf854d08fa083
msm: clock-krait-8974: Fall back to safest PVS when table not found

If there is new hardware that uses unexpected PVS/Speed bin bits, we
should fall back to the safest PVS table instead of failing to probe.
Implement this fall back during clock-krait-8974 probe.

Change-Id: Ie2b06839cac7e5e63eb99df69f9a0aa20744c6c5
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>