Fix a race condition in sdram_controller

The following scenario could occur:

1. An AXI write burst is started.
2. The controller finishes one SDRAM write burst. AXI write
bursts are generally larger than SDRAM bursts, so it takes
several of the latter for each of the former.
3. The remainder of the AXI write data is queued in the
sdram_controller store fifo
4. An AXI read burst is started for the same address.
5. The controller starts the SDRAM read burst.  Read
bursts are prioritized above write bursts to fix issues
where the VGA controller was being starved.

Because the write burst hasn't been written to RAM yet,
the SDRAM read burst grabs stale data.

The fix is to check if there the SDRAM read and write addresses
are the same, and to prioritize writes only in this case
Fix link error due to incorrect library order
Use SDRAM controller by default for verilog simulation