msm_serial_hs: Dynamic allocation of port structures

This patch allocates the msm_hs_port structures
dynamically during probe and cleans up during exit.
The msm_hs_get_uart_port function now looks up the
uart_state data structure to find the right uart_port.

Change-Id: I3876959eb41173d2115d2c1acfc612b75ca2e46a
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
msm_serial_hs: Implement driver functionality to be closer to HW spec

Implement TX callflow to be in accordance with HW spec and make
sure TXEMT clock off logic is correct. On receiver side, issue
force stale interrupt and make sure upper layer get bytes upto
size of RX buffer

CRs-Fixed: 575119
Change-Id: Iee469b0ba489386b571a86897b62eae84ff34ca5
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm_serial_hs: Defensive checks

Add defensive checks in the APIs exposed to clients
and tty layer to avoid unclocked access

CRs-Fixed: 593860
Change-Id: Ibb80b18143a3b90156a7043fd66d4097f7c073e1
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Signed-off-by: Dilip Kota <c_dkota@codeaurora.org>
wcnss: Retry PIL on error ready timeout

When the first PIL on wcnss fails; and when it times out on smp2p
error ready, retry PIL a couple more times. We have seen instances where
wcnss does bootup on PIL retry.

CRs-Fixed: 613487
Change-Id: I92569559cb8022c831036ec50ccf2e7475f0278c
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
ASoC: msm: 8x10: Adjust button range for button 7

With very fast press of button 7, it is found that
the measured voltage falls few mv below the lower
threshold. Adjust the threshold to detect the button
press.

Change-Id: I2d23607df9b3b7e993da214961f25fbadcffd60c
CRs-Fixed: 611825
Signed-off-by: Simmi Pateriya <simmip@codeaurora.org>
ASoC: msm8x10: Add backend DAI Link for incall music delivery

A new backend DAI link is required for DSDA incall music
delivery. This is because two different voice sessions will
use different ports and backends.

Change-Id: Icff8676872d40094f49b52df8ee3219a2f3283cd
CRs-Fixed: 571380, 616154
Signed-off-by: Avinash Vaish <avaish@codeaurora.org>
qseecom: update clock ref count when bus scaling timer is running

When there are multiple enable/dislable clock operations, ce clock
ref count is not updated correctly when the timer to disable clock
is running. Specifically, the ref count is not decreased when the
old operation is finished and then we reset clock for the new enable
clock. Thus, the ce clock is not disabled after all operation are
completed due to incorrect clk ref count. We make a change to
decrease clock reference count before reset timer, when the timer
is running, then clock is disabled when all ce clock operations
finish and the timer expires.

Change-Id: If71fd526acd9a74bf21731841fae0b98e76a89b5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ARM: dts: msm8610: Add support for incall LCH tone playback

Add incall local call hold tone playback device required
for delivering LCH tone to the farside. A separate device
is required in the device tree for each different voice
session/subscription.

Change-Id: I6b723be6a025dba80f117c3032c4352952142fb8
CRs-Fixed: 571380, 616154
Signed-off-by: Avinash Vaish <avaish@codeaurora.org>
qseecom: change qseecom bus scaling timer operation

To ensure ce clock is not disabled before tz operation is completed,
we delete the old timer when tz side operation begins, and then add
a new timer after tz operation is completed.

Change-Id: I4bc8fe3d9305cc1ed5db8e6490832fcc790ef3d7
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
wcnss: Correct the logging sequence of certain registers

PMU_PLL_STATUS and PMU_CPU_AHB_CFG_RCGR registers should be dumped
despite common_ss being collapsed.

CRs-fixed: 615461
Change-Id: Iac7da726ad70420d29411e0c9f6bcd75c776ba50
Signed-off-by: Yue Ma <yuem@codeaurora.org>
msm: wcnss: Add the support to access IRIS registers using bit-bang

During cold boot, if firmware watchdog bite happens, WCNSS platform driver
will try to log Pronto registers, but in some cases it cannot access them
since there is no clock on Pronto. Add the support to log IRIS registers
using bit-bang in order to debug this issue.

CRs-fixed: 616588
Change-Id: I9315c295d33d131224605adddca26796de25e1fb
Signed-off-by: Yue Ma <yuem@codeaurora.org>
input: sensors: use work queue for mma8x5x data polling

Accelerometer mma8x5x driver register polling device for data
polling, but polling device only update polling interval on
new polling cycle, this will cause delay on change polling
interval in some case.

Change-Id: I391dc5507a40e6bfc7e8127a0db89cb685eaf192
Signed-off-by: Bingzhe Cai <bingzhec@codeaurora.org>
mmc: sdhci: add asynchronous interrupt support for sdio card

Some controllers can gate the clock to save power
even for SDIO cards. In such cases, an asynchronous
interrupt mechanism is used to receive interrupts
even when clocks are off.

This patch wakes up the sdio thread if interrupts
were received when clocks were off.

CRs-Fixed: 585481
Change-Id: Ifcfafad251dedc992637596b6bb9349cfbca5d8b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: core: add wakeup functionality to sdio cards

This patch initializes wakeup source if the detected card
is a sdio card and enables the wakeup capability.

Platform drivers would have to invoke:
 * pm_wakeup_event on this card device to signal a wakeup
 * corresponding pm_relax have to be invoked

CRs-Fixed: 585481
Change-Id: Ic8d5c98073e8ed3f676eb42fc0ce1f13a11cb40f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci: add sdio wakeup event

This patch adds wakeup event capability for sdio cards.
When a wakeup event is received during suspend, a reference
to the card devices' wakeup source is taken for 300 ms.

It is expected that the function driver would act on the
wakeup event within this time-period.

CRs-Fixed: 585481
Change-Id: I80fe0c450e8d9b3df51aa181d667d94517c961dc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci-msm: ignore data-end-bit error in 1 bit mode

Some SDHC controllers are unable to handle data end-bit
errors in one bit mode.
This patch adds a quirk to ignore data-end-bit error in
1-bit mode in Qualcomm SDHC controllers.

CRs-Fixed: 585481
Change-Id: Ica0f10573d654021449c32197b126e12bb1a3c10
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci-msm: add sdio wakeup support

This patch adds the sdio wakeup funtionality in either of the
two methods:

1. If a dedicated mpm interrupt is present in the particular
   slot, it is configured to be used as wakeup.

2. If dedicated mpm interrupt is absent for a slot, then
   DAT1 line gpio is configured as wakeup.

CRs-Fixed: 585481
Change-Id: Ide54f807c12262429011e245de7dcecadcc60f3b
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
ARM: dts: msm: add SDHC DAT1 line wakeup support for 8974

This patch adds mpm and gpio based wakeup interrupt support.
SDIO card interrupt can wake up the system by pulling the
DAT1 line low. When the system is suspended mpm monitors
this line and wakes up the system.

CRs-Fixed: 585481
Change-Id: I4ea5e29200e7138bca18ed429175a39414ea3318
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: quirks: enable clock gating for AR6004 card

This patch whitelists the AR6004 card for clock-gating.
The controller supports asynchronous interrupt functionality
which enables to receive interrupts from the card when clocks
are off. Hence, clocks can be turned off when idle.

This patch whitelists the card, to let the clock-gating
framework gate the clock during idle time.

CRs-Fixed: 585481
Change-Id: I651f86e42595cc82f99093c06ee220a1d0ec95a9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
mmc: sdhci: Use right API to read/write host control2 register

The SDHCI host control2 register offset is 0x3E which is not
word aligned and is only 16 bits wide. But we use readl/writel
to read/write to it. Use readw/writew to avoid any alignment
issues.

CRs-Fixed: 585481
Change-Id: Ibaa87ce46f2a2dd97f9e1c7979adb38e426acd5b
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>