Changes to constrains logic.

Everything now inherently list-based, even single bit signals.
Added ucf files

For snap and kc705. For use with ISE
Changes to ports

Create a port class
Added command line options to choose backend

Currently environment variables aren't set by
this variable -- it's just passed to the toolflow
instance builder.
Added ISEBackend class

Compiles using vivado, using tcl command.
Generates ucf files rather than xdc
Support for tengbe_v2 block

-- Added required "pcores"
-- Added yellow block python
-- Removed simulink block callback script. Only one port parameter now.
TODO: make allowed values of port reflect hardware platform
-- Changed gen_block_file script to evaluate matlab parameters
before saving them to yaml
Added 10gbe test model

Compiles OK on snap with vivado backend.
Fails with ISE backend -- problem with bram cores in in/out fifos
Changed instantiation of parameterless modules

vivado seems to handle

mymodule #(
) inst_name (
...

but ise (well, planahead) doesn't like it. Changed these to

mymodule inst_name (
...
Changed matlab license server tunneled port