mips_ejtag.c|h: use version specific IMPs

and make version specific debug log

Change-Id: I17f7ff757cfa1264a1dadbfe20c5e21de62ef87a
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1929
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
mips_ejtag.c: do not set v2.6 ECR bits on v2.0 devices

Change-Id: I894abbb923282d5f84daf8e0bca69190c07567de
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1930
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
mips32.c: fix IB and DB bits check for EJTAG v2.0

Change-Id: I4e28dddc1d5d9c2b923ae17beacdd7f73591b1d0
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1931
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
mips32.c: cache debug caps and support EJTAG 2.0 specific changes

EJTAG v2.0 indicated some debug caps in IMP register.
V2.6 moved them to DCR register. To make it more universal,
convert this values and store them for later use.

Change-Id: Id6b9f47c9c2ea94d37281ebfcae5acf357261ddf
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1932
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
mips_m4k.c: D or I breaks only if they supported.

For example Realtek RTL8186 (Lexra LX5280 core) don't
support break- and watchpoints.

Change-Id: Ie00102da4bf13a8c42a9ad05910c66884f297cfd
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1933
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
mips_m4k.c: EJTAGBOOT and NORMALBOOT are not supported on EJTAG 2.0

Change-Id: I8157c19e9d8aed5c2376a2c54c32c1ddac1ad5af
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1934
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
tcl/board/stm32ldiscovery: fix breakage

Change-Id: I450ea82c27009be6bad6a7814969d81964ff44d8
Signed-off-by: Eldar Khayrullin <eldar.khayrullin@mail.ru>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2255
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
tcl/interface/ftdi: auto-select SWD from converters' configs

When you source a JTAG-SWD converter config, any other transport
doesn't make any sense, so just autoselect it right there.

Change-Id: I6c098740905a0d4007473fc19cc07e11cbcc9369
Suggested-by: Хайруллин Эльдар <eldar.khayrullin@mail.ru>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2248
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Eldar Khayrullin <eldar.khayrullin@mail.ru>
transport: emit a warning when a user tries to reselect a transport

Even though changing transport is impossible, reselecting it should be
harmless.

Change-Id: I6c1c2786134e826f47f848b590e6d712b6fd2206
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2251
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
jtag: usb_blaster: fix initialization regression

As Daniel pointed out, since the rewrite of the USB Blaster driver, the
initialization behaviour has change. The initial flush of the FIFOs is
not longer done with a specific USB setup packet, but with a write
filling up the blaster queues.

The problem is, quoting Daniel :

    When the CPLD is in bit banging mode (as is usually the case), the
    first 0x00 byte sets all pins to low and disables the output
    driver. Disabling the output drivers is a few nanoseconds slower
    than changing a pin from high to low, so I see a spike towards GND
    on my reset line when that byte is sent over USB. The spike is too
    short to have an effect on the board.

    When the 4096 0x00 bytes are processed and the TMS=1 is to be
    generated, all I see is several microseconds of low level on all
    pins, resetting my board.

This patch changes the way the initialization is done :
 - at driver init, nothing is sent towards the usb-blaster
   This gives time for init script to setup PIN6 and PIN8 (resets)
 - at the very first driver command, the initialization is done :
   - the output is in bit bigbang mode
   - the PIN6 and PIN8 are computed according to init script
   - the 4096 computed output is sent

Change-Id: If7ceee957f6b59bcb27c8f912f1cfdd0f94f75ed
Reported-by: Daniel Glöckner <daniel-gl@gmx.net>
Cc: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/2229
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Daniel Glöckner <daniel-gl@gmx.net>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
flash/nor/stm32f1x: add STM32F302x6/8 IDs, clarify STM32F302xB/C

Change-Id: I22afbe30f32b0ea9b59c3de8d15ce14bdc4763cc
Reported-by: Luis Rodrigues <lfrodrigues@gmail.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2249
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
jlink: fix typo

Change-Id: If495b819c0532a97447ec7208c13d8a66a3ad47d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2243
Tested-by: jenkins
jlink: add variant "J-Link Lite-ADI"

Fitted to various Analog Devices ADuCM36x dev boards.

Change-Id: Ib3691704c0ecd2f8cba1abba284aee695d6bc135
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2244
Tested-by: jenkins
jlink: Constantify string arrays

Change-Id: Ib63f4c32e6d5a7dad21567521d938142ea40b308
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2245
Tested-by: jenkins
flash: samd: add missing ID for SAMD20E18A

This was somehow missed in the chip ID table and of course that's
exactly the one on my board (as such, tested on hardware).

Change-Id: I212d7c729d979e0357f1d4635f40935e25fe6ff3
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2260
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
jtag/drivers/ftdi: Use adapter_khz value for initial clock speed (was default 1kHz)

nrf51822 doesn't like a 1kHz initial clock rate, puts the DAP into a bad state.

Mailing list discussion thread: http://sourceforge.net/p/openocd/mailman/openocd-devel/thread/20140718081528.GA5554%40ex2.lan/#msg32621853

Change-Id: I71aa75505cc1b41ee80c7b9db415f6ac738c2916
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2223
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
stm32lx: refactor and add support for STM32L0xx

This adds initial support for the STM32L0 family, specifically the ID
code 417 variant.  The 'L0 has 128B rather than 256B pages as well as a
different number of pages per sector.  It also has several key registers
and register sets in different locations from the STM32L1xx parts.

This change therefore takes the opportunity to reorganize part information into
a const table (it was previously determined by a set of control statements) and
abstracts away some of the low-level details to make them generic for L1 and
L0 parts.

We also include the first bank's size (for dual bank parts) in the new
device information table (and correct that size for the 0x437 variant
which is 256 rather than 192KB).

The 'L0 parts will not use the built-in loader/helper for Flash writing.

Tested on STM32L053 (dicovery board and Nucleo board) and STM32L152
(discovery board).

Change-Id: I57f7a8ab02caee266de71b31ae82a50d85728a0b
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2200
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
target async loader: add offset to debug lines

This was very helpful when debugging programs during async loading.

Change-Id: Ia2eacc3e105403f70f51b1242b675e2ffe86e8ca
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2203
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
jtag: always configure enabled tap parameter appropriately

Commit f701c0cb seems to have introduced a regression for non-JTAG
transports as the newly created "tap" (DAP actually) ended up being
disabled, thus resulting in total lack of functionality.

This was exposed by a debug log demonstrating ftdi SWD transport
connection to mdr32f9q2i, the target wasn't examined on init and
couldn't be reset.

Change-Id: If53cbe800d4adc177aa3ac3219860e7fa15b3e49
Reported-by: Хайруллин Эльдар <eldar.khayrullin@mail.ru>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2261
Tested-by: jenkins
Reviewed-by: Angus Gratton <gus@projectgus.com>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
target/adi_v5_swd: fix segfault when calling jtag_to_swd

When SWD mode is not supported by the target adapter, the call should
return an error instead of segfaulting.

Change-Id: I1626097deb93ecfbe78a6e82d812c7a673dbbde5
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2256
Tested-by: jenkins