pinctrl: rockchip: fix non-hiword-mask registers on rk3288

On the rk3288 the pinctrl-related registers do not use the hiword-mask
paradigm (enabling the the corresponding bit for writing by setting
bit x+16 to 1). Instead these registers need common update operations.

In contrast the pull-settings residing in the pmu area on the rk3188 use
the hiword-mask paradigm and from what I heard, future SoCs are supposed
to use the hiword-mask in the complete pmu area, so this will hopefully
stay a one-off issue.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: set is_generic in pinconf_ops

The rockchip pinctrl driver implements the generic pinconfig, therefore
also state this, so that the default pinconf dump functions work.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: add separate type for rk3288

An upcoming pinctrl function of the rk3288 differs again from everything else,
so we'll need a separate type for it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: add drive-strength control for rk3288

The rk3288 is the first Rockchip soc handling the drive strength on a per-pin
basis, while the older ones can set the drive-strength only for specific
pin-groups. Therefore limit setting the drive-strength to this soc for now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent

In case the rate_hw does not implement determine_rate, but only round_rate
we fallback to best_parent selection if mux_hw is present and support
reparenting.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>

This also fixes a rate calculation problem when using the standard div and
mux ops, as in this case currently only the mux->determine_rate is used
in the composite rate calculation.
So when for example the composite clock has two parents at 600 and 800MHz,
the requested rate is 75MHz, which the divider could provide, without this
change the rate would be set 600MHz ignoring the divider completely.
This may be way out of spec for the component.

[fixed the output to actually return a rate instead of the diff]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>

on stih416 board
Tested-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
clk: composite: allow read-only clocks

This allows readl-only composite clocks by making mux_ops->set_parent and
divider_ops->round_rate/set_rate optional.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
clk: composite: improve rate_hw sanity check logic

The function pointer population and sanity checking logic got a bit ugly
with the advent of the .determine_rate callback. Clean it up.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
clk: rockchip: add basic infrastructure for clock branches

This adds infrastructure for registering clock branches. On Rockchip SoCs
most clock branches are a combination of mux,divider and gate components,
thus a composite clock is used when appropriate.

Clock branches are supposed to be declared in an array using the COMPOSITE*
or MUX, etc makros defined in the header and then registered using
rockchip_clk_register_branches.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
clk: rockchip: add clock type for pll clocks and pll used on rk3066

All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to
handle their plls:
                       |--\
xin32k ----------------|mux\
xin24m -----| pll |----|pll|--- pll output
       \---------------|src/
                       |--/

The pll output is sourced from 1 of 3 sources, the actual pll being one of
them. To change the pll frequency it is imperative to remux it to another
source beforehand. This is done by adding a clock-listener to the pll that
handles the remuxing before and after the rate change.

The output mux is implemented as a separate clock to make use of already
existing common-clock features for disabling the pll if one of the other
two sources is used.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
clk: rockchip: add reset controller

All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset-
controller for SoC peripherals in their clock controller.
While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change
register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary.
To be compatible with both schemes the reset controller takes a flag to
decide which scheme to use, similar to the other HIWORD_MASK flags used in the
clock framework.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
dt-bindings: add documentation for rk3188 clock and reset unit

This add bindings documentation for the clock and reset unit found on
rk3188 and rk3066 SoCs from Rockchip.

Also deprecate the old gate clock binding, as these shouldn't be used
in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
clk: rockchip: add clock driver for rk3188 and rk3066 clocks

This adds a clock driver that handles the specific muxes, dividers and gates
of rk3188 and rk3066 SoCs.

The structure of the clock list resembles the arrangement of their
counterparts in the clock architecture diagrams found in the SoC
documentation.

Clocks exported to the clock provider are currently limited to well known
or measured ones. So additional clock exports may be necessary in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
dt-bindings: add documentation for rk3288 cru

This adds the dt-binding documentation for the clock and reset unit found on
Rockchip rk3288 SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
clk: rockchip: add clock controller for rk3288

Add the clock tree definition for the new rk3288 SoC.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER

All known Rockchip SoCs have a reset controller in their CRUs, so it's
helpful to have the reset controller framework selected by default,
only be deselected by the user in special cases.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
ARM: dts: rockchip: add cru nodes and update device clocks to use it

This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and
also updates the device nodes retrieve their clocks from there, instead of
the previous gate clock nodes.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Max Schwarz <max.schwarz@online.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
ARM: dts: rockchip: move oscillator input clock into main dtsi

The clock definitions get a lot shorter due to the soc clocks being handled by
rk3188-cru and only the input clock remains. These can now simply live
in the main rk3xxx.dtsi without affecting readability.

At the same time, rename the node to oscillator, adding a clock-output-names
property to match how the rk3288 handles this.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Max Schwarz <max.schwarz@online.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
arm: dts: rockchip: remove obsolete clock gate definitions

The clock and reset unit is now provided by the rk3188-cru clock driver and thus
the old style definitions of the gate clocks can go away.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Max Schwarz <max.schwarz@online.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
ARM: dts: rockchip: remove soc subnodes

Comments received from the rk3288 submission indicated that a generic subnode
to group soc components should not be used.

So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
ARM: dts: rockchip: add handles for shared nodes that don't have one yet

Some nodes that are changed in the dtsi hierarchy do not have handles yet.
As it was suggested in the rk3288 submission to do subsequent nodes changes
through such handle-references, add the missing ones.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>