sunxi: Add new Merrii M2 (A20) board

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: Add i12-tvbox board

The i12 tvbox is an A20 based android tvbox, with 1G RAM, 4G nand flash,
ap6210 sdio wifi + bt (broadcom BCM43362 sdio wifi + uart attached brcm bt),
2USB host ports using USB-A receptacles and a micro-usb receptacle for USB OTG,
and 100Mbit ethernet.

The PCB is labelled i12-a20 hence I've named the board i12-a20. It is used
in noname allwinner A20 tv-boxes, which are sometimes sold with Q5 or
QT840A as product name.

Note this patch does NOT enable the ethernet port, as the phy-power is
controller through a gpio-pin (PH21) and we don't have support for having
a gpio power pin for the phy (yet) in the GMAC driver (nor in the EMAC one).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: axp209: Fix setting of ldo4 voltage

The logic was wrong, resulting in us always setting the ldo to its lowest
setting of 1.25V.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Revert "gpio: Oscillate option"

This reverts commits d104fc0ee38a and af9f4057a591.

Henrik says in https://groups.google.com/forum/#!msg/linux-sunxi/nSKH4IcTaX8/YBVQLMrzfKwJ:

    GPIO_OSCILLATE is a hack in our u-boot used for measuring PIO performance.
    Should likely be removed.

This is one less thing to worry about for upstreaming, or at least removes
something from the diff...

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
net/designware: call phy_connect_dev() to properly setup phylib device

This sets up the linkage from the phydev back to the ethernet device. This
symptom of not doing this which I noticed was:
    <NULL> Waiting for PHY auto negotiation to complete....
rather than:
    dwmac.1c50000 Waiting for PHY auto negotiation to complete....

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
net/designware: ensure device private data is DMA aligned.

struct dw_eth_dev contains fields which are accessed via DMA, so make sure it
is aligned to a dma boundary. Without this I see:
    ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
v2: Sign of with my own mail not my work mail. I made these changes on my
own time, but a .gitconfig vcsh mismerge caused "git commit -s" to use the
wrong thing. (I wondered why everyone was CCing me at work...)
net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN

This is required at least on ARM.

When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
v2: - collapsed "net/designware: align cache invalidation on rx" and
      "net/designware: invalidate entire descriptor in dw_eth_send" into
      one.
    - roundup sizeof(txrx_status) to ARCH_DMA_MINALIGN instead of just
      invalidating the entire descriptor.
net/designware: reorder struct dw_eth_dev to pack more efficiently.

The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.

Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.

The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
v3.1: Actually move to the head of the struct, like the commit log said...
v3: Also align tx and rx bufs
net/designware: Make DMA burst length configurable and reduce by default

The correct value for this setting can vary across SoCs and boards, so make it
configurable.

Also reduce the default value to 8, which is the same default as used in the
Linux driver.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
v3: Pulled into this series instead of sunxi series.
net/designware: Drop TXSECONDFRAME flag

This is a non sunxi related deviation we've from upstream. Drop it, if we want
this we should pursue this through upstream.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add U-Boot support for Olimex's A13-SOM

A13-SOM is Allwinner A13
based SOM with 512MB DDR3.
There is no AXP PMU.
Hardware:
 A13 SoC
 uSD card slot
 512MB DDR3
 4 connectors with 0.05inch step.

http://olimex.com
Signed-off-by: HeHoPMaJIeH <gamishev@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
uboot: add support for pcDuino3

This patchset adds u-boot support for pcDuino3. The board
has been stress-tested for clock=480 and FAST_MBUS, and
has proven to be stable so far.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: HYP/non-sec: move switch to non-sec to the last boot phase

Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: non-sec: reset CNTVOFF to zero

Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: add missing HYP mode constant

In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.

Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add separate section for secure code

In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.

Nothing is using it just yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: allow relocation to secure RAM

The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.

This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
  before entering the payload
- performing an exception return from secure mode directly into
  the payload
- allowing the code to be dynamically relocated to secure RAM
  before switching to non-secure.

This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add generic ARMv7 PSCI code

Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: HYP/non-sec: add the option for a second-stage monitor

Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>