verilog: Move variable declaration to top of function
verilog: Add isContainer function
verilog: Add verbose messages related to context
verilog: Allow context other than module
verilog: Reorganize context related code into functions

Also fixes context string generation.
verilog: Simplify main parser

Parser was skipping to known start/end-of-statement characters before
starting to find tags. When using named blocks, something like the
following can happen:

initial begin : myblock
  reg  var;

If the parser waits for ; to start searching for a new tag, then "var"
is missed.
verilog: Implement support for named begin..end blocks
verilog: Add support for Verilog 2001 parameter declaration
verilog: Add support for localparam
verilog: Ignore variable attribute "signed"
verilog: Add support for qualified tags
verilog: Improve test cases

Include a `define with value and a comma separated list of parameters.
Merge branch 'verilog' of https://github.com/vhda/ctags into fishman/master

Conflicts:
	verilog.c
units: Add named block tags to Verilog expected ouput