ARM: dts: mvebu: Introduce a new compatible for the PMSU node

The initial binding for PMSU were wrong. It didn't take into account
all the register from the PMSU and in the other hand refered to
registr which are not part of PMSU. This commit introduce a new
compatible for the PMSU node and mark the previous one as
obsolete. However we still continue to support it during a few release.

Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Allow to power down L2 cache controller in idle mode

This commit adds a function which adjusts the PMSU configuration to
automatically power down the L2 and coherency fabric when we enter a
certain idle state.

This feature is part of the Power Management Service Unit of the
Armada 370 and Armada XP SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Add the PMSU related part of the cpu idle functions

The cpu idle support will need to access to Power Management Service
Unit. This commit adds the prepare and restore functions that will be
used in the idle path of the cpuidle driver.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Set the start address of a CPU in a separate function

Setting the start (or boot) address of A CPU is no more used only
during SMP bring up, but will also be used by the CPU idle functions
or later by the CPU hot plug ones.

This commit moves it in a separate function.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Register notifier callback for the cpuidle transition

In order to have well encapsulated code use notifier callback for
CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC

Add the wfi, cpu idle and cpu deep idle power states support for the
Armada XP SoCs.

All the latencies and the power consumption values used at the
"armada_370_xp_idle_driver" structure are preliminary and will be
modified in the future after running some measurements and analysis.

Based on the work of Nadav Haklai.

Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: register the cpuidle driver for the Armada XP SoCs

The cpuidle is a platform driver so we to register the device just
after the initialization of the board in an arch_initcall.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
of: Allows to use the PCI translator without the PCI core

Translating an address from a PCI node of the device-tree into a CPU
physical address doesn't require the core PCI support. Those
translations are just related to the device tree itself.

The use case to translate an address from a PCI node without actually
using the PCI core support is when one needs to access the PCI
controller without accessing any PCI devices.

Marvell SoCs, such as Kirkwood, Dove or Armada XP for instance, come
with an IP of a PCI controller. In the registers of this controller
are stored the ID and the revision of a SoC. With this patch it will
be possible to read the SoC ID of a board without any PCI device and
then without the PCI core support.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Allows to get the SoC ID even without PCI enabled

The address translation of a PCI node don't require anymore the PCI
support in the kernel. This translation is mandatory to be able to
read the SoC ID which is stored in the PCI controller of the mvebu
SoCs.

This patch selects the symbol needed to get only this translation for
all the mvebu platforms.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
i2c: mv64xxx: refactor message start to ensure proper initialization

Because the offload mechanism can fall back to a standard transfer,
having two seperate initialization states is unfortunate. Let's just
have one state which does things consistently. This fixes a bug where
some preparation was missing when the fallback happened. And it makes
the code much easier to follow. To implement this, we put the check
if offload is possible at the top of the offload setup function.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: stable@vger.kernel.org # v3.12+
Fixes: 930ab3d403ae (i2c: mv64xxx: Add I2C Transaction Generator support)