Handle non 1/0 single-bit signals

It turns out Verilog has 4 values, whoops!
Check that VCDs can set the same value many times

It turns out this actually works fine, I was wrong about what the bug
was.
Handle skipped cycles in VCD files

It's completely reasonable for a VCD file to skip the cycle
deliminator when there's nothing to be done for a cycle.  This simple
handles that sort of behavior correctly rather than assuming that
every cycle was listed in the VCD file, even empty ones.
Handle VCD single-bit shortnames

VCD files apparently have a syntax feature in which a shortname can
refer to a single bit inside a larger multi-bit signal. VCD files
produced by ModelSim use this syntax. This commit adds support for that
into libvcd and vcddiff.