Fixed a crash in 16 bits when offset is bigger than 16 bits.

git-svn-id: http://distorm.googlecode.com/svn/trunk@246 d69571ce-fa96-11de-930f-d36749347e7b
Added segment register to be in Operand class as well as the instruction class.
Issue #69 closed.

git-svn-id: http://distorm.googlecode.com/svn/trunk@247 d69571ce-fa96-11de-930f-d36749347e7b
Some FPU instructions had generic MEM operand instead of specific FPUM16.
Issue 58 fixed.

git-svn-id: http://distorm.googlecode.com/svn/trunk@248 d69571ce-fa96-11de-930f-d36749347e7b
op->size is always real size of operand when it's sign extended imm32 in 64 bits.
Issue 76 fixed.

git-svn-id: http://distorm.googlecode.com/svn/trunk@249 d69571ce-fa96-11de-930f-d36749347e7b
Some typos were fixed (thanks to Visual Assist :)
And fixed support for RDRAND instruction (Issue 81).

git-svn-id: http://distorm.googlecode.com/svn/trunk@250 d69571ce-fa96-11de-930f-d36749347e7b